1Gb: x4, x8, x16 DDR SDRAM
Features
DDR SDRAM
MT46V256M4 – 64 Meg x 4 x 4 Banks
MT46V128M8 – 32 Meg x 8 x 4 Banks
MT46V64M16 – 16 Meg x 16 x 4 Banks
Features
Options
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR400)
• Bidirectional data strobe (DQS) transmitted/
received with data, that is, source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
(x16 has two – one per byte)
• Programmable burst lengths (BL): 2, 4, or 8
• Auto refresh and self refresh modes
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
• tRAS lockout supported (tRAP = tRCD)
Table 1:
Marking
• Configuration
– 256 Meg x 4 (64 Meg x 4 x 4 banks)
– 128 Meg x 8 (32 Meg x 8 x 4 banks)
– 64 Meg x 16 (16 Meg x 16 x 4 banks)
• Plastic package – OCPL
– 66-pin TSOP
(400-mil width, 0.65mm pin pitch)
– 66-pin TSOP (Pb-free)
(400-mil width, 0.65mm pin pitch)
• Timing – cycle time
– 5.0ns @ CL = 3 (DDR400B)
– 6.0ns @ CL = 2.5 (DDR333B)2
– 7.5ns @ CL = 2.5 (DDR266B)2
• Temperature rating
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
• Revision
256M4
128M8
64M16
TG
P
-5B1
-6T
-75
None
IT
:A
Notes: 1. Not recommended for new designs.
2. See Table 3 on page 2 for module
compatibility.
Key Timing Parameters
CL = CAS (READ) latency; data-out window is MIN clock rate with 50 percent duty cycle at CL = 2.5
Clock Rate (MHz)
Speed Grade
CL = 2
CL = 2.5
CL = 3
Data-Out
Window
Access
Window
DQS–DQ
Skew
-5B
-6T
-75
133
133
100
167
167
133
200
n/a
n/a
1.6ns
2.0ns
2.5ns
±0.70ns
±0.70ns
±0.75ns
+0.40ns
+0.45ns
+0.50ns
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Features
Table 2:
Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
Table 3:
Marking
256 Meg x 4
128 Meg x 8
64 Meg x 16
64 Meg x 4 x 4 banks
8K
16K (A0–A13)
4 (BA0, BA1)
4K (A0–A9, A11, A12)
32 Meg x 8 x 4 banks
8K
16K (A0–A13)
4 (BA0, BA1)
2K (A0–A9, A11)
16 Meg x 16 x 4 banks
8K
16K (A0–A13)
4 (BA0, BA1)
1K (A0–A9)
Speed Grade Compatibility
PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2)
-5B
Yes
Yes
Yes
Yes
Yes
Yes
-6T
–
Yes
Yes
Yes
Yes
Yes
-75
–
–
–
–
Yes
Yes
-5B
-6T
-75
-75
-75
-75
Figure 1:
1Gb DDR SDRAM Part Numbers
Example Part Number: MT46V64M16P-6T:A
MT46V
Configuration
Package
Speed
:
Sp.
Op. Temp. Revision
Revision
:A x4, x8, x16
Configuration
256 Meg x 4
256M4
128 Meg x 8
128M8
64 Meg x 16
Operating Temperature
Commercial
64M16
IT
Industrial
Package
400-mil TSOP
400-mil TSOP (Pb-free)
TG
Special Options
P
Standard
-6T
Speed Grade
tCK = 5ns, CL = 3
tCK = 6ns, CL = 2.5
-75
tCK = 7.5ns, CL = 2.5
-5B
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1Gb: x4, x8, x16 DDR SDRAM
Table of Contents
Table of Contents
State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Electrical Specifications – IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Electrical Specifications – DC and AC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
LOAD MODE REGISTER (LMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
ACTIVE (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
PRECHARGE (PRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
BURST TERMINATE (BST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
AUTO REFRESH (AR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
REGISTER DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Power-down (CKE Not Active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
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1Gb: x4, x8, x16 DDR SDRAM
State Diagram
State Diagram
Figure 2:
Simplified State Diagram
Power
applied
Power
on
PRE
Precharge
all banks
Self
refresh
LMR
REFS
REFSX
Idle
REFA
all banks
precharged
CKEL
LMR
MR
EMR
Auto
refresh
CKEH
Active
powerdown
Precharge
powerdown
ACT
CKE HIGH
CKE LOW
Row
active
Burst
stop
READ
WRITE
BST
WRITE
WRITE A
READ A
READ
Write
WRITE A
READ A
PRE
Write A
READ
Read
READ A
PRE
PRE
Read A
Precharge
PREALL
PRE
Automatic sequence
Command sequence
ACT = ACTIVE
BST = BURST TERMINATE
CKEH = Exit power-down
CKEL = Enter power-down
EMR = Extended mode register
LMR = LOAD MODE REGISTER
MR = Mode register
Note:
PRE = PRECHARGE
PREALL = PRECHARGE all banks
READ A = READ with auto precharge
REFA = AUTO REFRESH
REFS = Enter self refresh
REFSX = Exit self refresh
WRITE A = WRITE with auto precharge
This diagram represents operations within a single bank only and does not capture concurrent operations in other banks.
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1Gb: x4, x8, x16 DDR SDRAM
Functional Description
Functional Description
The DDR SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or
write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The x16 offering has two data strobes,
one for the lower byte and one for the upper byte.
The DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which may then
be followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8
locations. An auto precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs
allows for concurrent operation, thereby providing high effective bandwidth by hiding
row precharge and activation time.
An auto refresh mode is provided, along with a power-saving power-down mode. All
inputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputs
are SSTL_2, Class II compatible.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL-enabled mode of operation.
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated
otherwise. Additionally, the x16 is divided into two bytes, the lower byte and upper
byte. For the lower byte (DQ0–DQ7) DM refers to LDM and DQS refers to LDQS. For
the upper byte (DQ8–DQ15) DM refers to UDM and DQS refers to UDQS.
• Complete functionality is described throughout the document and any page or
diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
• Any specific requirement takes precedence over a general statement.
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©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Functional Block Diagrams
Functional Block Diagrams
The 1Gb DDR SDRAM is a high-speed CMOS, dynamic random access memory
containing 1,073,741,824 bits. It is internally configured as a 4-bank DRAM.
Figure 3:
256 Meg x 4 Functional Block Diagram
CKE
CK#
CK
Command
decode
CS#
WE#
CAS#
RAS#
Control
logic
Bank 3
Bank 2
Bank 1
Mode registers
Refresh
counter
16
13
Rowaddress
MUX
14
14
Bank 0
rowaddress
latch
and
decoder
16,384
CK
Bank 0
memory
array
(16,384 x 2,048 x 8)
DLL
Data
4
8
READ
latch
Sense amplifierS
4
MUX
DRVRS
4
1
DQS
generator
(16,384)
DQ0–DQ3
Column 0
I/O gating
DM mask logic
2
A0–A13,
BA0, BA1
16
Address
register
2
1
DQS
1
Mask
2048
Column
decoder
12
8
Bank
control
logic
Columnaddress
counter/
latch
DQS
Input
registers
11
8
WRITE
FIFO
and
drivers
CK
out
CK
in
1
1
1
4
4
4
4
2
8
RCVRS
DM
4
Data
CK
1
Column 0
1
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1Gb: x4, x8, x16 DDR SDRAM
Functional Block Diagrams
Figure 4:
128 Meg x 8 Functional Block Diagram
CKE
CK#
CK
Command
decode
CS#
WE#
CAS#
RAS#
Control
logic
Bank 3
Bank 2
Bank 1
Refresh
counter
Mode registers
13
Rowaddress
MUX
16
14
14
Bank 0
rowaddress
16,384
latch
&
decoder
CK
Bank 0
memory
array
(16,384 x 1,024 x 16)
DLL
Data
8
16
READ
latch
SENSE AMPLIFIERS
8
MUX
DRVRS
8
1
DQS
generator
(16,384)
DQ0–DQ7
Column 0
I/O gating
DM mask logic
2
A0–A13,
BA0, BA1
16
Address
register
Bank
control
logic
2
DQS
1
1
Mask
10
1
1
1
8
8
8
8
2
RCVRS
16
DM
8
CLK
Data
in
CLK
out
Column
decoder
Columnaddress
counter/
latch
WRITE
FIFO
and
drivers
16
1024
11
DQS
Input
registers
16
CK
1
Column 0
1
Figure 5:
64 Meg x 16 Functional Block Diagram
CKE
CK#
CK
Command
decode
CS#
WE#
CAS#
RAS#
Control
logic
Bank 3
Bank 2
Bank 1
Mode registers
Refresh
counter
16
13
Rowaddress
MUX
14
14
Bank 0
rowaddress
16,384
latch
&
decoder
CK
Bank 0
memory
array
(16,384 x 512 x 32)
DLL
Data
16
32
READ
latch
SENSE AMPLIFIERS
16
MUX
DRVRS
16
2
DQS
generator
(16,384)
DQ0–DQ15
Column 0
I/O gating
DM mask logic
2
A0–A13,
BA0, BA1
16
Address
register
2
Bank
control
logic
Column
decoder
Columnaddress
counter/
latch
DQS L/H
2
2
2
2
16
16
16
16
Mask
512
10
DQS
Input
registers
32
9
32
WRITE
FIFO
and
drivers
CK
out
CK
in
2
4
32
RCVRS
LDM, UDM
32
Data
CK
1
Column 0
1
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1Gb_DDR_x4x8x16_D2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
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1Gb: x4, x8, x16 DDR SDRAM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Figure 6:
66-pin TSOP Pin Assignments (Top View)
x4
x16
x8
VDD
VDD
VDD
NF
DQ0
DQ0
VDDQ
VDDQ VDDQ
NC
DQ1
NC
DQ0
DQ1
DQ2
VSSQ
VSSQ
VSSQ
NC
DQ3
NC
NF
DQ2
DQ4
VDDQ
VDDQ VDDQ
NC
NC
DQ5
DQ1
DQ3
DQ6
VSSQ
VSSQ
VssQ
NC
DQ7
NC
NC
NC
NC
VDDQ
VDDQ VDDQ
NC
NC LDQS
A13
A13
A13
VDD
VDD
VDD
DNU
DNU
DNU
NC
NC
LDM
WE#
WE#
WE#
CAS#
CAS# CAS#
RAS#
RAS# RAS#
CS#
CS#
CS#
NC
NC
NC
BA0
BA0
BA0
BA1
BA1
BA1
A10/AP A10/AP A10/AP
A0
A0
A0
A1
A1
A1
A2
A2
A2
A3
A3
A3
VDD
VDD
VDD
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2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
8
x16
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
DNU
VREF
VSS
UDM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x8
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x4
VSS
NF
VSSQ
NC
DQ3
VDDQ
NC
NF
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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1Gb: x4, x8, x16 DDR SDRAM
Pin Assignments and Descriptions
Table 4:
Pin Descriptions
TSOP
Numbers
Symbol
Type
Description
29, 30, 31, 32,
35, 36, 37, 38,
39, 40, 28,
41, 42, 17
A0, A1, A2, A3,
A4, A5, A6, A7,
A8, A9, A10,
A11, A12, A13
Input
26, 27
BA0, BA1
Input
45, 46
CK, CK#
Input
44
CKE
Input
24
CS#
Input
47
20, 47
DM
LDM, UDM
Input
23, 22,
21
2, 4, 5, 7,
8, 10, 11, 13,
54, 56, 57, 59,
60, 62, 63, 65
2, 5, 8, 11,
56, 59, 62, 65
5, 11, 56, 62
51
16
51
RAS#, CAS#,
WE#
DQ0–DQ3
DQ4–DQ7
DQ8–DQ11
DQ12–DQ15
DQ0–DQ3
DQ4–DQ7
DQ0–DQ3
DQS
LDQS
UDQS
Input
I/O
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands,
to select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the
PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or
all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE REGISTER (LMR) command.
Bank address inputs: BA0 and BA1 define the bank to which an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. BA0 and BA1 also
define which mode register (mode register or extended mode register) is
loaded during the LOAD MODE REGISTER command.
Clock: CK and CK# are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK and
the negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal
clock, input buffers, and output drivers. Taking CKE LOW provides
PRECHARGE power-down and SELF REFRESH operations (all banks idle) or
ACTIVE power-down (row active in any bank). CKE is synchronous for
power-down entry and exit and for self refresh entry. CKE is asynchronous
for self refresh exit and for disabling the outputs. CKE must be maintained
HIGH throughout read and write accesses. Input buffers (excluding CK, CK#,
and CKE) are disabled during power-down. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an
LVCMOS LOW level after VDD is applied and until CKE is first brought
HIGH, after which it becomes a SSTL_2 input only.
Chip select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
Input data mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a
write access. DM is sampled on both edges of DQS. Although DM pins are
input-only, the DM loading is designed to match that of DQ and DQS pins.
For the x16, LDM is DM for DQ0–DQ7 and UDM is DM for DQ8–DQ15. Pin 20
is a NC on x4 and x8.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Data input/output: Data bus for x16.
I/O
Data input/output: Data bus for x8.
I/O
I/O
1, 18, 33
3, 9, 15, 55, 61
VDD
VDDQ
Supply
Supply
Data input/output: Data bus for x4.
Data strobe: Output with read data, input with write data. DQS is edgealigned with read data, center-aligned with write data. It is used to capture
data. For the x16, LDQS is DQS for DQ0–DQ7 and UDQS is DQS for DQ8–
DQ15. Pin 16 is NC on x4 and x8.
Power supply.
DQ power supply: Isolated on the die for improved noise immunity.
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1Gb: x4, x8, x16 DDR SDRAM
Pin Assignments and Descriptions
Table 4:
Pin Descriptions (continued)
TSOP
Numbers
34, 48, 66
6, 12, 52, 58, 64
49
14, 25, 43, 53
4, 7, 10, 13, 14,
16, 20, 25, 43,
53, 54, 57, 60,
63
4, 7, 10, 13, 14,
16, 20, 25, 43,
53, 54, 57, 60,
63
2, 8, 59, 65
19, 50
Symbol
Type
VSS
VSSQ
VREF
NC
NC
Supply
Supply
Supply
–
–
NC
–
No connect for x4: These pins should be left unconnected.
NF
DNU
–
–
No function for x4: These pins should be left unconnected.
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1Gb_DDR_x4x8x16_D2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Description
Ground.
DQ ground: Isolated on the die for improved noise immunity.
SSTL_2 reference voltage.
No connect for x16: These pins should be left unconnected.
No connect for x8: These pins should be left unconnected.
Do not use: Must float to minimize noise on VREF.
10
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1Gb: x4, x8, x16 DDR SDRAM
Package Dimensions
Package Dimensions
Figure 7:
66-Pin Plastic TSOP (400 mil)
See detail A
22.22 ± 0.08
0.71
0.65 TYP
0.10 (2X)
0.32 ± .075 TYP
11.76 ±0.20
10.16 ±0.08
+0.03
0.15 –0.02
Pin #1 ID
Gage plane
0.10
0.25
+0.10
–0.05
0.10
0.80 TYP
1.20 MAX
0.50 ±0.10
Detail A
Notes:
1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
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1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – IDD
Electrical Specifications – IDD
Table 5:
IDD Specifications and Conditions (x4, x8)
Notes 1–5, 11, 13, 15, 47 apply to the entire table; Notes appear on page 26–31; See also Table 7 on page 14;
VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V (-5B); VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V (-6T, -75);
0°C ≤ TA ≤ +70°C
Parameter/Condition
Operating one-bank active-precharge current:
t
RC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
Symbol
-5B
-6T
-75
Units
Notes
IDD0
165
160
145
mA
23, 48
IDD1
200
195
180
mA
23, 48
IDD2P
13
10
10
mA
24, 33
IDD2F
70
65
60
mA
51
IDD3P
40
35
30
mA
24, 33
IDD3N
55
50
45
mA
23
IDD4R
225
220
200
mA
23, 48
IDD4W
235
230
210
mA
23
IDD5
IDD5A
IDD6
IDD7
345
13
10
530
340
10
9
525
330
10
9
485
mA
mA
mA
mA
50
28, 50
12
23, 49
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
Operating one-bank active-read-precharge current:
BL = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA;
Address and control inputs changing once per clock cycle
Precharge power-down standby current: All banks
idle; Power-down mode; tCK = tCK (MIN); CKE = LOW
Idle standby current: CS# = HIGH; All banks are idle;
t
CK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle. VIN = VREF for DQ,
DQS, and DM
Active power-down standby current: One bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One
bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM,
and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst
reads; One bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); IOUT = 0mA
Operating burst write current: BL = 2; Continuous
burst writes; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM,
and DQS inputs changing twice per clock cycle
Auto refresh burst current:
Self refresh current: CKE ≤ 0.2V
tREFC
= tRFC (MIN)
tREFC = 7.8µs
Standard
Operating bank interleave read current: Four bank
interleaving READs (BL = 4) with auto precharge;
t
RC = MIN; tCK = tCK (MIN); Address and control inputs
change only during ACTIVE, READ, or WRITE commands
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1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – IDD
Table 6:
IDD Specifications and Conditions (x16)
Notes 1–5, 11, 13, 15, 47 apply to the entire table; Notes appear on page 26–31; See also Table 7 on page 14;
VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V (-5B); VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V (-6T, -75);
0°C ≤ TA ≤ +70°C
Parameter/Condition
Symbol
-5B
-6T
-75
Units
Notes
IDD0
170
165
145
mA
23, 48
IDD1
215
210
195
mA
23, 48
IDD2P
15
10
10
mA
24, 33
IDD2F
70
65
60
mA
51
IDD3P
40
35
30
mA
24, 33
IDD3N
55
50
45
mA
23
IDD4R
280
270
245
mA
23, 48
IDD4W
285
275
250
mA
23
tREFC
IDD5
tREFC
IDD5A
IDD6
IDD7
345
15
10
545
340
10
9
535
330
10
9
495
mA
mA
mA
mA
50
28, 50
12
23, 49
Operating one-bank active-precharge current:
t
RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
Operating one-bank active-read-precharge current:
BL = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA;
Address and control inputs changing once per clock cycle
Precharge power-down standby current: All banks
idle; Power-down mode; tCK = tCK (MIN); CKE = LOW
Idle standby current: CS# = HIGH; All banks are idle;
t
CK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle. VIN = VREF for DQ,
DQS, and DM
Active power-down standby current: One bank
active; Power-down mode; tCK = tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One
bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM,
and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst
reads; One bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); IOUT = 0mA
Operating burst write current: BL = 2; Continuous
burst writes; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM,
and DQS inputs changing twice per clock cycle
Auto refresh burst current:
Self refresh current: CKE ≤ 0.2V
= tRFC (MIN)
= 7.8µs
Standard
Operating bank interleave read current: Four bank
interleaving READs (BL = 4) with auto precharge;
t
RC = MIN; tCK = tCK (MIN); Address and control inputs
change only during ACTIVE, READ, or WRITE commands
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1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – IDD
Table 7:
IDD Test Cycle Times
Values reflect number of clock cycles for each test
IDD Test
IDD0
IDD1
IDD4R
IDD4W
IDD5
IDD5A
IDD7
Speed
Grade
Clock Cycle
Time
-75
-6T
-5B
-75
-6T
-5B
-75
-6T
-5B
-75
-6T
-5B
-75
-6T
-5B
-75
-6T
-5B
-75
-6T
-5B
7.5ns
6.0ns
5.0ns
7.5ns
6.0ns
5.0ns
7.5ns
6.0ns
5.0ns
7.5ns
6.0ns
5.0ns
7.5ns
6.0ns
5.0ns
7.5ns
6.0ns
5.0ns
7.5ns
6.0ns
5.0ns
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1Gb_DDR_x4x8x16_D2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
t
RRD
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
2
2
2
t
RCD
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
3
3
3
t
RAS
t
t
6
7
8
6
7
8
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
3
3
3
3
3
3
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
3
3
3
9
10
11
9
10
11
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
10
10
11
14
RP
RC
t
RFC
t
REFI
CL
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
16
20
24
16
20
24
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
16
20
24
1,026
1,182
1,414
n/a
n/a
n/a
n/a
n/a
n/a
2.5
2.5
3
2.5
2.5
3
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
2.5
2.5
3
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1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Electrical Specifications – DC and AC
Stresses greater than those listed in Table 8 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 8:
Absolute Maximum Ratings
Parameter
Min
Max
Units
VDD supply voltage relative to VSS
VDDQ supply voltage relative to VSS
VREF and inputs voltage relative to VSS
I/O pins voltage relative to VSS
Storage temperature (plastic)
Short circuit output current
–1V
–1V
–1V
–0.5V
–55
–
+3.6V
+3.6V
+3.6V
VDDQ + 0.5V
+150
50
V
V
V
V
°C
mA
Table 9:
DC Electrical Characteristics and Operating Conditions (-5B)
Notes: 1–5 and 17 apply to the entire table; Notes appear on page 26; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V
Parameter/Condition
Supply voltage
I/O supply voltage
I/O reference voltage
I/O termination voltage (system)
Input high (logic 1) voltage
Input low (logic 0) voltage
Input leakage current:
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.35V
(All other pins not under test = 0V)
Output leakage current:
(DQ are disabled; 0V ≤ VOUT ≤ VDDQ)
Full-drive option output
High current (VOUT =
levels: (x4, x8, x16)
VDDQ - 0.373V, minimum
Reduced-drive option
output levels: (x16 only)
Ambient operating
temperatures
VREF, minimum VTT)
Low current (VOUT =
0.373V, maximum VREF,
maximum VTT)
High current (VOUT =
VDDQ - 0.373V, minimum
VREF, minimum VTT)
Low current (VOUT =
0.763V, maximum VREF,
maximum VTT)
Symbol
Min
Max
Units
Notes
VDD
VDDQ
VREF
VTT
VIH(DC)
VIL(DC)
II
+2.5
+2.5
0.49 × VDDQ
VREF - 0.04
VREF + 0.15
–0.3
–2
+2.7
+2.7
0.51 × VDDQ
VREF + 0.04
VDD + 0.3
VREF - 0.15
+2
V
V
V
V
V
V
µA
37, 42
37, 42, 45
7, 45
8, 45
29
29
IOZ
–5
+5
µA
IOH
–16.8
–
mA
IOL
+16.8
–
mA
IOHR
–9
–
mA
IOLR
+9
–
mA
TA
TA
0
–40
+70
+85
°C
°C
Commercial
Industrial
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15
38, 40
39, 40
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1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 10:
DC Electrical Characteristics and Operating Conditions (-6T, -75)
Notes: 1–5, 17 apply to the entire table; Notes appear on page 26; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Parameter/Condition
Supply voltage
I/O supply voltage
I/O reference voltage
I/O termination voltage (system)
Input high (logic 1) voltage
Input low (logic 0) voltage
Input leakage current:
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.35V
(All other pins not under test = 0V)
Output leakage current:
(DQ are disabled; 0V ≤ VOUT ≤ VDDQ)
Full-drive option output
High current (VOUT =
levels: (x4, x8, x16)
VDDQ - 0.373V, minimum
Reduced-drive option
output levels: (x16 only)
Ambient operating
temperatures
Table 11:
VREF, minimum VTT)
Low current (VOUT =
0.373V, maximum VREF,
maximum VTT)
High current (VOUT =
VDDQ - 0.763V, minimum
VREF, minimum VTT)
Low current (VOUT =
0.763V, maximum VREF,
maximum VTT)
Symbol
Min
Max
Units
Notes
VDD
VDDQ
VREF
VTT
VIH(DC)
VIL(DC)
II
+2.3
+2.3
0.49 × VDDQ
VREF - 0.04
VREF + 0.15
–0.3
–2
+2.7
+2.7
0.51 × VDDQ
VREF + 0.04
VDD + 0.3
VREF - 0.15
+2
V
V
V
V
V
V
µA
37, 42
37, 42, 45
7, 45
8, 45
29
29
IOZ
–5
+5
µA
IOH
–16.8
–
mA
IOL
+16.8
–
mA
IOHR
–9
–
mA
IOLR
+9
–
mA
TA
TA
0
–40
+70
+85
°C
°C
Commercial
Industrial
38, 40
39, 40
AC Input Operating Conditions
Notes: 1–5, 17 apply to the entire table; Notes appear on page 26;
0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V (VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V for -5B)
Parameter/Condition
Symbol
Min
Max
Units
Notes
Input high (logic 1) voltage
Input low (logic 0) voltage
I/O reference voltage
VIH(AC)
VIL(AC)
VREF(AC)
VREF + 0.310
–
0.49 × VDDQ
–
VREF - 0.310
0.51 × VDDQ
V
V
V
15, 29, 41
15, 29, 41
7
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1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Figure 8:
Input Voltage Waveform
VDDQ (2.3V MIN)
VOH (MIN) (1.670V1 for SSTL_2 termination)
System noise margin (power/ground,
crosstalk, signal integrity attenuation)
1.560V
VIH(AC)
1.400V
VIH(DC)
1.300V
1.275V
1.250V
1.225V
1.200V
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
1.100V
VIL(DC)
0.940V
VIN(AC) - provides margin
between VOL (MAX)
and VIL(AC)
VOL (MAX) (0.83V2 for SSTL_2
VIL(AC)
Receiver
termination)
VssQ
Transmitter
Notes:
1. VOH (MIN) with test load is 1.927V.
2. VOL (MAX) with test load is 0.373V.
3. Numbers in diagram reflect nominal values utilizing circuit below for all devices other than
-5B.
VTT
25Ω
25Ω
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Reference
point
17
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©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 12:
Clock Input Operating Conditions
Notes: 1–5, 16, 17, 31 apply to the entire table; Notes appear on page 26;
0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V (VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V for -5B)
Parameter/Condition
Symbol
Min
Max
Units
Notes
Clock input mid-point voltage: CK and CK#
Clock input voltage level: CK and CK#
Clock input differential voltage: CK and CK#
Clock input differential voltage: CK and CK#
Clock input crossing point voltage: CK and CK#
VMP(DC)
VIN(DC)
VID(DC)
VID(AC)
VIX(AC)
1.15
–0.3
0.36
0.7
0.5 × VDDQ - 0.2
1.35
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.5 × VDDQ + 0.2
V
V
V
V
V
7, 10
7
7, 9
9
10
Figure 9:
SSTL_2 Clock Input
Maximum clock level1
2.80V
CK#
X
1.45V
3
VMP(DC)2 VIX(AC)
1.25V
1.05V
4
VID(DC)
5
VID(AC)
X
CK
Minimum clock level1
–0.30V
Notes:
1.
2.
3.
4.
5.
6.
7.
CK or CK# may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.
This provides a minimum of 1.15V to a maximum of 1.35V and is always half of VDDQ.
CK and CK# must cross in this region.
CK and CK# must meet at least VID(DC) MIN when static and is centered around VMP(DC).
CK and CK# must have a minimum 700mV peak-to-peak swing.
For AC operation, all DC clock requirements must also be satisfied.
Numbers in diagram reflect nominal values for all devices other than -5B.
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 13:
Capacitance (x4, x8 TSOP)
Note: 14 applies to the entire table; Notes appear on page 26
Parameter
Delta input/output capacitance: DQ0–DQ3 (x4), DQ0–DQ7 (x8)
Delta input capacitance: Command and address
Delta input capacitance: CK, CK#
Input/output capacitance: DQ, DQS, DM
Input capacitance: Command and address
Input capacitance: CK, CK#
Input capacitance: CKE
Table 14:
Symbol
Min
Max
Units
Notes
DCIO
DCI1
DCI2
CIO
CI1
CI2
CI3
–
–
–
4.0
2.0
2.0
2.0
0.50
0.50
0.25
5.0
3.0
3.0
3.0
pF
pF
pF
pF
pF
pF
pF
25
30
30
Symbol
Min
Max
Units
Notes
DCIOL
DCIOU
DCI1
DCI2
CIO
CI1
CI2
CI3
–
–
–
–
4.0
2.0
2.0
2.0
0.50
0.50
0.50
0.25
5.0
3.0
3.0
3.0
pF
pF
pF
pF
pF
pF
pF
pF
25
25
30
30
Capacitance (x16 TSOP)
Note: 14 applies to the entire table; Notes appear on page 26
Parameter
Delta input/output capacitance: DQ0–DQ7, LDQS, LDM
Delta input/output capacitance: DQ8–DQ15, UDQS, UDM
Delta input capacitance: Command and address
Delta input capacitance: CK, CK#
Input/output capacitance: DQ, LDQS, UDQS, LDM, UDM
Input capacitance: Command and address
Input capacitance: CK, CK#
Input capacitance: CKE
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 15:
Electrical Characteristics and Recommended AC Operating Conditions (-5B)
Notes 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26;
0°C ≤ TA ≤ +70°C; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V
AC Characteristics
-5B
Parameter
Access window of DQ from CK/CK#
CK high-level width
Clock cycle time
Symbol
t
AC
tCH
t
CK (3)
(2.5)
t
CK (2)
t
CL
tDH
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDS
tDSH
tDSS
tHP
tHZ
tIH
F
tIPW
tIS
F
tLZ
tMRD
tQH
CL = 3
CL = 2.5
CL = 2
tCK
CK low-level width
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS–DQ skew, DQS to last DQ valid, per group, per access
WRITE command to first DQS latching transition
DQ and DM input setup time relative to DQS
DQS falling edge from CK rising – hold time
DQS falling edge to CK rising – setup time
Half-clock period
Data-out High-Z window from CK/CK#
Address and control input hold time (slew rate ≥0.5 V/ns)
Address and control input pulse width (for each input)
Address and control input setup time (slew rate ≥0.5 V/ns)
Data-out Low-Z window from CK/CK#
LOAD MODE REGISTER command cycle time
DQ–DQS hold, DQS to first DQ to go non-valid, per access
tQHS
Data hold skew factor
ACTIVE-to-READ with auto precharge command
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE/AUTO REFRESH command period
ACTIVE-to-READ or WRITE delay
REFRESH-to-REFRESH command
1Gb
interval
AUTO REFRESH command period
1Gb
Average periodic refresh interval
1Gb
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
Terminating voltage delay to VDD
DQS write preamble
DQS write preamble setup time
DQS write postamble
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
tRAP
tRAS
tRC
tRCD
t
REFC
tRFC
tREFI
t
RP
RPRE
tRPST
tRRD
tVTD
t
WPRE
tWPRES
tWPST
t
20
Min
Max
Units
–0.70
0.45
5
6
7.5
0.45
0.40
1.75
–0.60
0.35
0.35
–
0.72
0.40
0.2
0.2
tCH,tCL
–
0.60
2.2
0.60
–0.70
10
tHP tQHS
–
15
40
55
15
–
+0.70
0.55
7.5
13
13
0.55
–
–
+0.60
–
–
0.40
1.28
–
–
–
–
+0.70
–
–
–
–
–
–
0.50
–
70,000
–
–
70.3
ns
ns
ns
ns
ns
µs
120
–
15
0.9
0.4
10
0
0.25
0
0.4
–
7.8
–
1.1
0.6
–
–
–
–
0.6
ns
µs
ns
t
CK
tCK
ns
ns
t
CK
ns
tCK
Notes
ns
tCK
ns
ns
ns
t
CK
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
31
52
46, 52
46, 52
31
27, 32
32
26, 27
27, 32
35
19, 43
15
15
19, 43
26, 27
36
24
50
24
44
44
21, 22
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 15:
Electrical Characteristics and Recommended AC Operating Conditions (-5B) (continued)
Notes 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26;
0°C ≤ TA ≤ +70°C; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V
AC Characteristics
-5B
Parameter
Symbol
t
WR
Write recovery time
Internal WRITE-to-READ command delay
Exit SELF REFRESH-to-non-READ
1Gb
command
Exit SELF REFRESH-to-READ command
Data valid output window
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
tWTR
t
XSNR
tXSRD
n/a
21
Min
Max
Units
15
2
126
–
–
–
tCK
200
–
t
QH - tDQSQ
Notes
ns
ns
tCK
ns
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 16:
Electrical Characteristics and Recommended AC Operating Conditions (-6T)
Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26;
0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
AC Characteristics
-6T (TSOP)
Parameter
Symbol
t
AC
Access window of DQ from CK/CK#
CK high-level width
Clock cycle time
CL = 2.5
CL = 2
CK low-level width
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS–DQ skew, DQS to last DQ valid, per group, per access
WRITE command to first DQS latching transition
DQ and DM input setup time relative to DQS
DQS falling edge from CK rising - hold time
DQS falling edge to CK rising - setup time
Half-clock period
tCH
t
CK (2.5)
tCK (2)
t
CL
t
DH
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDS
tDSH
tDSS
tHP
t
HZ
Data-out High-Z window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input pulse width (for each input)
Address and control input setup time (fast slew rate)
Address and control input setup time (slow slew rate)
Data-out Low-Z window from CK/CK#
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
tIH
F
tIH
S
tIPW
tIS
S
tLZ
tMRD
tQH
t
QHS
Data hold skew factor
ACTIVE-to-READ with auto precharge command
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE/AUTO REFRESH command period
ACTIVE-to-READ or WRITE delay
REFRESH-to-REFRESH command
1Gb
interva
Average periodic refresh interval 1Gb
AUTO REFRESH command period 1Gb
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
Terminating voltage delay to VSS
DQS write preamble
DQS write preamble setup time
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
F
tIS
tRAP
tRAS
tRC
t
RCD
REFC
t
tREFI
tRFC
t
RP
tRPRE
tRPST
tRRD
tVTD
t
WPRE
tWPRES
22
Min
Max
Units
–0.70
0.45
6
7.5
0.45
0.45
1.75
–0.6
0.35
0.35
–
0.75
0.45
0.2
0.2
tCH,
tCL
–
0.75
0.8
2.2
0.75
0.8
–0.7
12
tHP tQHS
–
15
42
60
15
–
+0.70
0.55
13
13
0.55
–
–
+0.6
–
–
0.45
1.25
–
–
–
–
+0.7
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.55
–
70,000
–
–
70.3
ns
ns
ns
ns
ns
µs
–
120
15
0.9
0.4
12
0
0.25
0
7.8
–
–
1.1
0.6
–
–
–
–
µs
ns
ns
tCK
tCK
ns
ns
t
CK
ns
Notes
ns
tCK
ns
ns
t
CK
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
tCK
ns
31
46, 52
46, 52
31
27, 32
32
26, 27
27, 32
35
19, 43
15
15
19, 43
26, 27
36, 54
24
24
50
44
44
21, 22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 16:
Electrical Characteristics and Recommended AC Operating Conditions (-6T) (continued)
Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26;
0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
AC Characteristics
-6T (TSOP)
Parameter
Symbol
t
DQS write postamble
Write recovery time
Internal WRITE-to-READ command delay
Exit SELF REFRESH-to-non-READ
1Gb
command
Exit SELF REFRESH-to-READ command
Data valid output window
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
23
Min
Max
WPST
tWR
t
WTR
tXSNR
0.4
15
1
126
t
200
–
t
QH - tDQSQ
XSRD
n/a
0.6
–
–
–
Units
t
CK
ns
t
CK
ns
Notes
20
t
CK
ns
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 17:
Electrical Characteristics and Recommended AC Operating Conditions (-75)
Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26;
0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
AC Characteristics
-75
Parameter
Access window of DQ from CK/CK#
CK high-level width
Clock cycle time
Symbol
t
AC
tCH
CL = 2.5
CL = 2
CK low-level width
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS–DQ skew, DQS to last DQ valid, per group, per access
WRITE command-to-first DQS latching transition
DQ and DM input setup time relative to DQS
DQS falling edge from CK rising – hold time
DQS falling edge to CK rising – setup time
Half-clock period
Data-out High-Z window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input pulse width (for each input)
Address and control input setup time (fast slew rate)
Address and control input setup time (slow slew rate)
Data-out Low-Z window from CK/CK#
LOAD MODE REGISTER command cycle time
DQ–DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE-to-READ with auto precharge command
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE/AUTO REFRESH command period
ACTIVE-to-READ or WRITE delay
REFRESH-to-REFRESH command interval
Average periodic refresh interval
AUTO REFRESH command period
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
Terminating voltage delay to VDD
DQS write preamble
DQS write preamble setup time
DQS write postamble
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
t
CK (2.5)
tCK (2)
t
CL
t
DH
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDS
tDSH
tDSS
tHP
tHZ
tIH
F
tIH
S
tIPW
tIS
F
tIS
S
tLZ
tMRD
tQH
tQHS
tRAP
tRAS
tRC
t
RCD
1Gb
1Gb
1Gb
tREFC
tREFI
tRFC
t
RP
RPRE
tRPST
t
RRD
tVTD
t
WPRE
tWPRES
tWPST
t
24
Min
Max
–0.75
0.45
7.5
10
0.45
0.5
1.75
–0.75
0.35
0.35
–
0.75
0.5
0.2
0.2
tCH,tCL
–
0.90
1
2.2
0.90
1
–0.75
15
tHP tQHS
–
20
40
65
20
–
–
120
20
0.9
0.4
15
0
0.25
0
0.4
+0.75
0.55
13
13
0.55
–
–
+0.75
–
–
0.5
1.25
–
–
–
–
+0.75
–
–
–
–
–
–
–
–
0.75
–
120,000
–
–
70.3
7.8
–
–
1.1
0.6
–
–
–
–
0.6
Units
Notes
ns
tCK
ns
ns
t
CK
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
t
CK
tCK
ns
ns
t
CK
ns
tCK
31
46
46
31
27, 32
32
26, 27
27, 32
35
19, 43
15
15
19, 43
26, 27
36
24
24
50
44
44
21, 22
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 17:
Electrical Characteristics and Recommended AC Operating Conditions (-75) (continued)
Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26;
0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
AC Characteristics
-75
Parameter
Symbol
Write recovery time
Internal WRITE-to-READ command delay
Exit SELF REFRESH-to-non-READ command
Exit SELF REFRESH-to-READ command
Data valid output window
Table 18:
t
WR
tWTR
1Gb
t
XSNR
tXSRD
n/a
Min
Max
15
–
1
–
127.5
–
200
–
t
QH - tDQSQ
Units
Notes
ns
tCK
ns
tCK
ns
26
Input Slew Rate Derating Values for Addresses and Commands
Note: 15 applies to the entire table; Notes appear on page 26;
0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Speed
Slew Rate
tIS
tIH
Units
-75
-75
-75
0.500 V/ns
0.400 V/ns
0.300 V/ns
1.00
1.05
1.10
1
1
1
ns
ns
ns
Table 19:
Input Slew Rate Derating Values for DQ, DQS, and DM
Note: 32 applies to the entire table; Notes appear on page 26;
0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Speed
Slew Rate
tDS
tDH
Units
-75
-75
-75
0.500 V/ns
0.400 V/ns
0.300 V/ns
0.50
0.55
0.60
0.50
0.55
0.60
ns
ns
ns
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and the
device operation are guaranteed for the full voltage range specified.
3. Outputs (except for IDD measurements) measured with equivalent load:
VTT
Output
(VOUT)
50Ω
Reference
point
30pF
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#),
and parameter specifications are guaranteed for the specified AC input levels under
normal use conditions. The minimum slew rate for the input signals used to test the
device is 1 V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 standard (that
is, the receiver will effectively switch as a result of the signal crossing the AC input
level and will remain in that state as long as the signal does not ring back above
[below] the DC input LOW [HIGH] level).
6. All speed grades are not offered on all densities. Refer to page 1 for availability.
7. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in
the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not
exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC
error and an additional ±25mV for AC noise. This measurement is to be taken at the
nearest VREF bypass capacitor.
8. VTT is not applied directly to the device. VTT is a system supply for signal termination
resistors, it is expected to be set equal to VREF, and it must track variations in the DC
level of VREF.
9. VID is the magnitude of the difference between the input level on CK and the input
level on CK#.
10. The value of VIX and VMP is expected to equal VDDQ/2 of the transmitting device and
must track variations in the DC level of the same.
11. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle times at CL = 3 for -5B; CL = 2.5, -6T/-75 speeds with the outputs
open.
12. Enables on-chip refresh and address counters.
13. IDD specifications are tested after the device is properly initialized and is averaged at
the defined cycle rate.
14. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS,
f = 100 MHz, TA = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.2V. DM input is
grouped with I/O pins, reflecting the fact that they are matched in loading.
15. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If the slew rate is
less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each
100 mV/ns reduction in slew rate from the 500 mV/ns. tIH has 0ps added, that is, it
remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For -5B
and -6T, slew rates must be greater than or equal to 0.5 V/ns.
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
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©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
16. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
VREF.
17. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including self
refresh mode, VREF must be powered within specified range. Exception: during the
period before VREF stabilizes, CKE < 0.3 × VDD is recognized as LOW.
18. The output timing reference level, as measured at the timing reference point (indicated in Note 3), is VTT.
19. tHZ and tLZ transitions occur in the same access time windows as data valid transitions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (High-Z) or begins driving (Low-Z).
20. The intent of the “Don’t Care” state after completion of the postamble is the DQSdriven signal should either be HIGH, LOW, or High-Z, and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions HIGH (above VIH[DC] MIN) then it must not transition LOW (below
VIH[DC] prior to tDQSH [MIN]).
21. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
22. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on tDQSS.
23. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the
minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS.
24. The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs
(15.625µs for 128Mb DDR). However, an AUTO REFRESH command must be asserted
at least once every 70.3µs (140.6µs for 128Mb DDR); burst refreshing or posting by the
DRAM controller greater than 8 REFRESH cycles is not allowed.
25. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
26. The data valid window is derived by achieving other specifications: tHP (tCK/2),
tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55, because functionality is
uncertain when operating beyond a 45/55 ratio. The data valid window derating
curves are provided in Figure 10 on page 28 for duty cycles ranging between 50/50
and 45/55.
27. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7;
x16 = LDQS with DQ0–DQ7 and UDQS with DQ8–DQ15.
28. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
during the REFRESH command period (tRFC [MIN]), else CKE is LOW (that is, during
standby).
29. To maintain a valid level, the transitioning edge of the input must:
29a. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
29b. Reach at least the target AC level.
29c. After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
30. The input capacitance per pin group will not differ by more than this maximum
amount for any given device.
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©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
31. CK and CK# input slew rate must be ≥1 V/ns (≥2 V/ns if measured differentially).
Figure 10:
Derating Data Valid Window (tQH – tDQSQ)
-6T @ tCK = 7.5ns
-75E / -75 @ tCK = 7.5ns
3.0ns
2.75
Data Valid Window
2.5ns
2.50
2.10
2.71
2.46
2.07
2.68
2.43
2.04
2.0ns
2.00
1.5ns
1.60
1.97
1.58
1.94
1.55
-6 @ tCK = 6ns
-6T @ tCK = 6ns
2.64
2.39
2.01
1.91
1.53
2.60
2.56
2.35
2.31
1.98
1.95
1.88
1.85
1.50
1.48
-5B @ tCK = 5ns
2.53
2.28
1.92
1.82
1.45
2.49
2.24
1.89
1.79
1.43
2.45
2.20
1.86
1.76
1.40
2.41
2.16
1.83
1.73
1.38
2.38
2.13
1.80
1.70
1.35
1.0ns
50/50
49/51
48/53
47/53
46/54
45/55
Clock Duty Cycle
32. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If
the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must
be added to tDS and tDH for each 100 mV/ns reduction in slew rate. For -5B and
-6T speed grades, the slew rate must be ≥0.5 V/ns. If the slew rate exceeds 4 V/ns,
functionality is uncertain.
33. VDD must not vary more than 4 percent if CKE is not active while any bank is active.
34. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by
the same amount.
35. tHP (MIN) is the lesser of tCL (MIN) and tCH (MIN) actually applied to the device CK
and CK# inputs, collectively, during bank active.
36. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN)
can be satisfied prior to the internal PRECHARGE command being issued.
37. Any positive glitch must be less than 1/3 of the clock cycle and not more than +400mV
or 2.9V (+300mV or 2.9V maximum for -5B), whichever is less. Any negative glitch
must be less than 1/3 of the clock cycle and not exceed either –300mV or 2.2V (2.4V for
-5B), whichever is more positive. The average cannot be below the +2.5V (2.6V for -5B)
minimum.
38. Normal output drive curves:
38a. The full driver pull-down current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of
Figure 11 on page 29.
38b. The driver pull-down current variation, within nominal voltage and temperature
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 11 on page 29.
38c. The full driver pull-up current variation from MIN to MAX process; temperature
and voltage will lie within the outer bounding lines of the V-I curve of Figure 12 on
page 29.
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©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
38d. The driver pull-up current variation within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the
V-I curve of Figure 12 on page 29.
38e. The full ratio variation of MAX to MIN pull-up and pull-down current should be
between 0.71 and 1.4 for drain-to-source voltages from 0.1V to 1.0V at the same
voltage and temperature.
38f. The full ratio variation of the nominal pull-up to pull-down current should be
unity ±10 percent for device drain-to-source voltages from 0.1V to 1.0V.
Figure 11:
Full Drive Pull-Down Characteristics
160
140
120
IOUT (mA)
100
80
60
40
20
0
0.0
0.5
1.0
1.5
2.0
1.5
2.0
2.5
VOUT (V)
Figure 12:
Full Drive Pull-Up Characteristics
0
-20
-40
IOUT (mA)
-60
-80
-100
-120
-140
-160
-180
-200
0.0
0.5
1.0
2.5
VDDQ - VOUT (V)
39. Reduced output drive curves:
39a. The full driver pull-down current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of
Figure 13 on page 30.
39b. The driver pull-down current variation, within nominal voltage and temperature
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 13 on page 30.
39c. The full driver pull-up current variation from MIN to MAX process; temperature
and voltage will lie within the outer bounding lines of the V-I curve of Figure 14.
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
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©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
39d. The driver pull-up current variation, within nominal voltage and temperature
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 14 on page 30.
39e. The full ratio variation of the MAX-to-MIN pull-up and pull-down current should
be between 0.71 and 1.4 for device drain-to-source voltages from 0.1V to 1.0V at
the same voltage and temperature.
39f. The full ratio variation of the nominal pull-up to pull-down current should be
unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
Figure 13:
Reduced Drive Pull-Down Characteristics
80
70
60
IOUT (mA)
50
40
30
20
10
0
0 .0
0 .5
1.0
1.5
2.0
2.5
VOUT (V)
Figure 14:
Reduced Drive Pull-Up Characteristics
0
-10
-20
IOUT (mA)
-30
-40
-50
-60
-70
-80
0.0
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
40. The voltage levels used are derived from a minimum VDD level and the referenced test
load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values.
41. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width ≤ 3ns, and the pulse
width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = –1.5V
for a pulse width ≤ 3ns, and the pulse width can not be greater than 1/3 of the cycle
rate.
42. VDD and VDDQ must track each other.
43. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
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1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
44. tRPST end point and tRPRE begin point are not referenced to a specific voltage level
but specify when the device output is no longer driving (tRPST) or begins driving
(tRPRE).
45. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V.
Alternatively, VTT may be 1.35V maximum during power-up, even if VDD/VDDQ are 0V,
provided a minimum of 42Ω of series resistance is used between the VTT supply and
the input pin.
46. The current Micron part operates below 83 MHz (slowest specified JEDEC operating
frequency). As such, future die may not reflect this option.
47. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
48. Random address is changing; 50 percent of data is changing at every transfer.
49. Random address is changing; 100 percent of data is changing at every transfer.
50. CKE must be active (HIGH) during the entire time a REFRESH command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC has been satisfied.
51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid HIGH or LOW logic level.
IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to
remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
52. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset followed by 200 clock cycles before any READ command.
53. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz.
Any noise above 20 MHz at the DRAM generated from any source other than that of
the DRAM itself may not exceed the DC voltage range of 2.6V ±100mV.
54. The -6T speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns
at any slower frequency.
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1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 20:
Normal Output Drive Characteristics
Characteristics are specified under best, worst, and nominal process variation/conditions
Pull-Down Current (mA)
Pull-Up Current (mA)
Voltage
(V)
Nominal
Low
Nominal
High
Min
Max
Nominal
Low
Nominal
High
Min
Max
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
6.0
12.2
18.1
24.1
29.8
34.6
39.4
43.7
47.5
51.3
54.1
56.2
57.9
59.3
60.1
60.5
61.0
61.5
62.0
62.5
62.8
63.3
63.8
64.1
64.6
64.8
65.0
6.8
13.5
20.1
26.6
33.0
39.1
44.2
49.8
55.2
60.3
65.2
69.9
74.2
78.4
82.3
85.9
89.1
92.2
95.3
97.2
99.1
100.9
101.9
102.8
103.8
104.6
105.4
4.6
9.2
13.8
18.4
23.0
27.7
32.2
36.8
39.6
42.6
44.8
46.2
47.1
47.4
47.7
48.0
48.4
48.9
49.1
49.4
49.6
49.8
49.9
50.0
50.2
50.4
50.5
9.6
18.2
26.0
33.9
41.8
49.4
56.8
63.2
69.9
76.3
82.5
88.3
93.8
99.1
103.8
108.4
112.1
115.9
119.6
123.3
126.5
129.5
132.4
135.0
137.3
139.2
140.8
–6.1
–12.2
–18.1
–24.0
–29.8
–34.3
–38.1
–41.1
–43.8
–46.0
–47.8
–49.2
–50.0
–50.5
–50.7
–51.0
–51.1
–51.3
–51.5
–51.6
–51.8
–52.0
–52.2
–52.3
–52.5
–52.7
–52.8
–7.6
–14.5
–21.2
–27.7
–34.1
–40.5
–46.9
–53.1
–59.4
–65.5
–71.6
–77.6
–83.6
–89.7
–95.5
–101.3
–107.1
–112.4
–118.7
–124.0
–129.3
–134.6
–139.9
–145.2
–150.5
–155.3
–160.1
–4.6
–9.2
–13.8
–18.4
–23.0
–27.7
–32.2
–36.0
–38.2
–38.7
–39.0
–39.2
–39.4
–39.6
–39.9
–40.1
–40.2
–40.3
–40.4
–40.5
–40.6
–40.7
–40.8
–40.9
–41.0
–41.1
–41.2
–10.0
–20.0
–29.8
–38.8
–46.8
–54.4
–61.8
–69.5
–77.3
–85.2
–93.0
–100.6
–108.1
–115.5
–123.0
–130.4
–136.7
–144.2
–150.5
–156.9
–163.2
–169.6
–176.0
–181.3
–187.6
–192.9
–198.2
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 21:
Reduced Output Drive Characteristics
Characteristics are specified under best, worst, and nominal process variation/conditions
Pull-Down Current (mA)
Pull-Up Current (mA)
Voltage
(V)
Nominal
Low
Nominal
High
Min
Max
Nominal
Low
Nominal
High
Min
Max
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3.4
6.9
10.3
13.6
16.9
19.9
22.3
24.7
26.9
29.0
30.6
31.8
32.8
33.5
34.0
34.3
34.5
34.8
35.1
35.4
35.6
35.8
36.1
36.3
36.5
36.7
36.8
3.8
7.6
11.4
15.1
18.7
22.1
25.0
28.2
31.3
34.1
36.9
39.5
42.0
44.4
46.6
48.6
50.5
52.2
53.9
55.0
56.1
57.1
57.7
58.2
58.7
59.2
59.6
2.6
5.2
7.8
10.4
13.0
15.7
18.2
20.8
22.4
24.1
25.4
26.2
26.6
26.8
27.0
27.2
27.4
27.7
27.8
28.0
28.1
28.2
28.3
28.3
28.4
28.5
28.6
5.0
9.9
14.6
19.2
23.6
28.0
32.2
35.8
39.5
43.2
46.7
50.0
53.1
56.1
58.7
61.4
63.5
65.6
67.7
69.8
71.6
73.3
74.9
76.4
77.7
78.8
79.7
–3.5
–6.9
–10.3
–13.6
–16.9
–19.4
–21.5
–23.3
–24.8
–26.0
–27.1
–27.8
–28.3
–28.6
–28.7
–28.9
–28.9
–29.0
–29.2
–29.2
–29.3
–29.5
–29.5
–29.6
–29.7
–29.8
–29.9
–4.3
–7.8
–12.0
–15.7
–19.3
–22.9
–26.5
–30.1
–33.6
–37.1
–40.3
–43.1
–45.8
–48.4
–50.7
–52.9
–55.0
–56.8
–58.7
–60.0
–61.2
–62.4
–63.1
–63.8
–64.4
–65.1
–65.8
–2.6
–5.2
–7.8
–10.4
–13.0
–15.7
–18.2
–20.4
–21.6
–21.9
–22.1
–22.2
–22.3
–22.4
–22.6
–22.7
–22.7
–22.8
–22.9
–22.9
–23.0
–23.0
–23.1
–23.2
–23.2
–23.3
–23.3
–5.0
–9.9
–14.6
–19.2
–23.6
–28.0
–32.2
–35.8
–39.5
–43.2
–46.7
–50.0
–53.1
–56.1
–58.7
–61.4
–63.5
–65.6
–67.7
–69.8
–71.6
–73.3
–74.9
–76.4
–77.7
–78.8
–79.7
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
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1Gb: x4, x8, x16 DDR SDRAM
Commands
Commands
Tables 22 and 23 provide a quick reference of available commands. Two additional Truth
Tables—Table 24 on page 35 and Table 25 on page 36—provide current state/next state
information.
Table 22:
Truth Table 1 – Commands
CKE is HIGH for all commands shown except SELF REFRESH; All states and sequences not shown are illegal or
reserved
Function
CS#
RAS#
CAS#
WE#
Address
Notes
H
L
L
L
L
L
L
L
X
H
L
H
H
H
L
L
X
H
H
L
L
H
H
L
X
H
H
H
L
L
L
H
X
X
Bank/row
Bank/col
Bank/col
X
Code
X
1
1
2
3
3
4
5
6, 7
L
L
L
L
Op-code
8
DESELECT
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (select bank and column and start READ burst)
WRITE (select bank and column and start WRITE burst)
BURST TERMINATE
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(enter self refresh mode)
LOAD MODE REGISTER
Notes:
Table 23:
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide bank address and A0–An (128Mb: n = 11; 256Mb and 512Mb: n = 12; 1Gb:
n = 13) provide row address.
3. BA0–BA1 provide bank address; A0–Ai provide column address, (where Ai is the most significant column address bit for a given density and configuration, see Table 2 on page 2) A10
HIGH enables the auto precharge feature (non persistent), and A10 LOW disables the auto
precharge feature.
4. Applies only to READ bursts with auto precharge disabled; this command is undefined (and
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0–BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing while in self refresh mode, all inputs and
I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0
select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–An provide the op-code to be written to the selected
mode register.
Truth Table 2 – DM Operation
Used to mask write data, provided coincident with the corresponding data
Name (Function)
DM
DQ
Write enable
Write inhibit
L
H
Valid
X
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Commands
Table 24:
Truth Table 3 – Current State Bank n – Command to Bank n
Notes: 1–6 apply to the entire table; Notes appear below
Current State
Any
Idle
Row active
Read
(auto precharge
disabled)
Write
(auto precharge
disabled)
CS#
RAS# CAS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Notes:
X
H
L
L
L
H
H
L
H
H
L
H
H
H
L
X
H
H
L
L
L
L
H
L
L
H
H
L
L
H
WE#
X
H
H
H
L
H
L
L
H
L
L
L
H
L
L
Command/Action
Notes
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
7
7
10
10
8
10
10, 12
8
9
10, 11
10
8, 11
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 27 on page 38) and
after tXSNR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (that is, the current state is for a specific
bank and the commands shown are those allowed to be issued to that bank when in that
state). Exceptions are covered in the notes below.
3. Current state definitions:
• Idle: The bank has been precharged, and tRP has been met.
• Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
• Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
• Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 24 and according to Table 25 on
page 36.
• Precharging: Starts with registration of a PRECHARGE command and ends when tRP is
met. Once tRP is met, the bank will be in the idle state.
• Row activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. Once tRCD is met, the bank will be in the “row active” state.
• Read with auto precharge enabled: Starts with registration of a READ command with
auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
• Write with auto precharge enabled: Starts with registration of a WRITE command with
auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
• Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC
is met. Once tRFC is met, the DDR SDRAM will be in the all banks idle state.
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Commands
• Accessing mode register: Starts with registration of an LMR command and ends when
t
MRD has been met. Once tMRD is met, the DDR SDRAM will be in the all banks idle
state.
6.
7.
8.
9.
10.
11.
12.
Table 25:
• Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
t
RP is met. Once tRP is met, all banks will be in the idle state.
All states and sequences not shown are illegal or reserved.
Not bank-specific; requires that all banks are idle, and bursts are not in progress.
May or may not be bank-specific; if multiple banks are to be precharged, each must be in a
valid state for precharging.
Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of
bank.
READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
Requires appropriate DM masking.
A WRITE command may be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.
Truth Table 4 – Current State Bank n – Command to Bank m
Notes: 1–6 apply to the entire table; Notes appear on page 36
Current State
CS#
Any
Idle
Row activating, active, or
precharging
Read (auto precharge disabled)
Write (auto precharge
disabled)
Read (with auto-precharge)
Write (with auto-precharge)
Notes:
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS# CAS# WE# Command/Action
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
Notes
7
7
7
7, 9
7, 8
7
7
7, 9
7
7
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 27 on page 38) and
after tXSNR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted (that is, the current state
is for bank n, and the commands shown are those allowed to be issued to bank m, assuming
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Commands
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
3. Current state definitions:
• Idle: The bank has been precharged, and tRP has been met.
• Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
• Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
• Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
• Read with auto precharge enabled: See note 3a below.
• Write with auto precharge enabled: See note 3a below.
a. The read with auto precharge enabled or write with auto precharge enabled states
can each be broken into two parts: the access period and the precharge period. For
read with auto precharge, the precharge period is defined as if the same burst was
executed with auto precharge disabled and then followed with the earliest possible
PRECHARGE command that still accesses all of the data in the burst. For write with
auto precharge, the precharge period begins when tWR ends, with tWR measured as
if auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. This device supports
concurrent auto precharge such that when a read with auto precharge is enabled or
a write with auto precharge is enabled, any command to other banks is allowed, as
long as that command does not interrupt the read or write data transfer already in
process. In either case, all other related limitations apply (for example, contention
between read data and write data must be avoided).
b. The minimum delay from a READ or WRITE command with auto precharge enabled,
to a command to a different bank is summarized in Table 26.
Table 26:
Command Delays
CLRU = CL rounded up to the next integer
From
Command
WRITE with auto
precharge
READ with auto
precharge
To Command
Minimum Delay
with Concurrent Auto Precharge
READ or READ with auto precharge
WRITE or WRITE with auto precharge
PRECHARGE
ACTIVE
READ or READ with auto precharge
WRITE or WRITE with auto precharge
PRECHARGE
ACTIVE
[1 + (BL/2)] × tCK + tWTR
(BL/2) × tCK
1 tCK
1 tCK
(BL/2) × tCK
[CLRU + (BL/2)] × tCK
1 tCK
1 tCK
4. AUTO REFRESH and LMR commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the “Command/Action” column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.
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Commands
Table 27:
Truth Table 5 – CKE
Notes 1–6 apply to the entire table; Notes appear below
CKEn-1
CKEn
Current State
Commandn
Actionn
Notes
L
L
L
H
Power-down
Self refresh
Power-down
Self refresh
All banks idle
Bank(s) active
All banks idle
X
X
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTO REFRESH
See Table 22 on page 34
Maintain power-down
Maintain self refresh
Exit power-down
Exit self refresh
Precharge power-down entry
Active power-down entry
Self refresh entry
7
H
L
H
H
Notes:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. CKE must not drop LOW during a column access. For a READ, this means CKE must stay
HIGH until after the read postamble time (tRPST); for a WRITE, CKE must stay HIGH until the
write recovery time (tWR) has been met.
6. Once initialized, including during self refresh mode, VREF must be powered within the specified range.
7. Upon exit of the self refresh mode, the DLL is automatically enabled. A minimum of 200
clock cycles is needed before applying a READ command for the DLL to lock. DESELECT or
NOP commands should be issued on any clock edges occurring during the tXSNR period.
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in
progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to
perform a NOP (CS# is LOW with RAS#, CAS#, and WE# are HIGH). This prevents
unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.
LOAD MODE REGISTER (LMR)
The mode registers are loaded via inputs A0–An (see "REGISTER DEFINITION" on page
46). The LMR command can only be issued when all banks are idle, and a subsequent
executable command cannot be issued until tMRD is met.
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Commands
ACTIVE (ACT)
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access, like a read or a write, as shown in Figure 15. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0–An selects the row.
Figure 15:
Activating a Specific Row in a Specific Bank
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Address
BA0, BA1
Row
Bank
Don’t Care
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Commands
READ
The READ command is used to initiate a burst read access to an active row, as shown in
Figure 16 on page 40. The value on the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0–Ai (where Ai is the most significant column address bit for a given
density and configuration, see Table 2 on page 2) selects the starting column location.
Figure 16:
READ Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Address
Col
EN AP
A10
DIS AP
BA0, BA1
Bank
Don’t Care
Note:
EN AP = enable auto precharge; DIS AP = disable auto precharge.
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Commands
WRITE
The WRITE command is used to initiate a burst write access to an active row as shown in
Figure 17. The value on the BA0, BA1 inputs selects the bank, and the address provided
on inputs A0–Ai (where Ai is the most significant column address bit for a given density
and configuration, see Table 2 on page 2) selects the starting column location.
Figure 17:
WRITE Command
CK#
CK
CKE HIGH
CS#
RAS#
CAS#
WE#
Address
Col
EN AP
A10
DIS AP
BA0, BA1
Bank
Don’t Care
Note:
EN AP = enable auto precharge; and DIS AP = disable auto precharge.
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Commands
PRECHARGE (PRE)
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks as shown in Figure 18. The value on the BA0, BA1 inputs selects
the bank, and the A10 input selects whether a single bank is precharged or whether all
banks are precharged.
Figure 18:
PRECHARGE Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Address
All banks
A10
One bank
BA0, BA1
Bank1
Don’t Care
Notes:
1. If A10 is HIGH, bank address becomes “Don’t Care”.
BURST TERMINATE (BST)
The BURST TERMINATE command is used to truncate READ bursts (with auto
precharge disabled). The most recently registered READ command prior to the BURST
TERMINATE command will be truncated, as shown in “Operations” on page 43. The
open page from which the READ burst was terminated remains open.
AUTO REFRESH (AR)
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous
to CAS#-before-RAS# (CBR) refresh in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All banks must be idle before an
AUTO REFRESH command is issued.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the
rest of the system is powered down. The SELF REFRESH command is initiated like an
AUTO REFRESH command except CKE is disabled (LOW).
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Operations
Operations
INITIALIZATION
Prior to normal operation, DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures, other than those specified, may result in
undefined operation.
To ensure device operation, the DRAM must be initialized as described in the following
steps:
1. Simultaneously apply power to VDD and VDDQ.
2. Apply VREF and then VTT power. VTT must be applied after VDDQ to avoid device latchup, which may cause permanent damage to the device. Exept for CKE, inputs are not
recognized as valid until after VREF is applied.
3. Assert and hold CKE at a LVCMOS logic LOW. Maintaining an LVCMOS LOW level on
CKE during power-up is required to ensure that the DQ and DQS outputs will be in
the High-Z state, where they will remain until driven in normal operation (by a read
access).
4. Provide stable clock signals.
5. Wait at least 200µs.
6. Bring CKE HIGH, and provide at least one NOP or DESELECT command. At this
point, the CKE input changes from a LVCMOS input to a SSTL_2 input only and will
remain a SSTL_2 input unless a power cycle occurs.
7. Perform a PRECHARGE ALL command.
8. Wait at least tRP time; during this time NOPs or DESELECT commands must be given.
9. Using the LMR command, program the extended mode register (E0 = 0 to enable the
DLL and E1 = 0 for normal drive; or E1 = 1 for reduced drive and E2–En must be set to
0 [where n = most significant bit]).
10. Wait at least tMRD time; only NOPs or DESELECT commands are allowed.
11. Using the LMR command, program the mode register to set operating parameters
and to reset the DLL. At least 200 clock cycles are required between a DLL reset and
any READ command.
12. Wait at least tMRD time; only NOPs or DESELECT commands are allowed.
13. Issue a PRECHARGE ALL command.
14. Wait at least tRP time; only NOPs or DESELECT commands are allowed.
15. Issue an AUTO REFRESH command. This may be moved prior to step 13.
16. Wait at least tRFC time; only NOPs or DESELECT commands are allowed.
17. Issue an AUTO REFRESH command. This may be moved prior to step 13.
18. Wait at least tRFC time; only NOPs or DESELECT commands are allowed.
19. Although not required by the Micron device, JEDEC requires an LMR command to
clear the DLL bit (set M8 = 0). If an LMR command is issued, the same operating
parameters should be utilized as in step 11.
20. Wait at least tMRD time; only NOPs or DESELECT commands are supported.
21. At this point the DRAM is ready for any valid command. At least 200 clock cycles with
CKE HIGH are required between step 11 (DLL RESET) and any READ command.
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Operations
Figure 19:
INITIALIZATION Flow Diagram
Step
1
VDD and VDDQ ramp
2
Apply VREF and VTT
3
CKE must be LVCMOS LOW
4
Apply stable CLOCKs
5
Wait at least 200µs
6
Bring CKE HIGH with a NOP command
7
PRECHARGE ALL
8
Assert NOP or DESELECT for tRP time
9
Configure extended mode register
10
Assert NOP or DESELECT for tMRD time
11
Configure load mode register and reset DLL
12
Assert NOP or DESELECT for tMRD time
13
PRECHARGE ALL
14
Assert NOP or DESELECT for tRP time
15
Issue AUTO REFRESH command
16
Assert NOP or DESELECT commands for tRFC
17
Issue AUTO REFRESH command
18
Assert NOP or DESELECT for tRFC time
19
Optional LMR command to clear DLL bit
20
Assert NOP or DESELECT for tMRD time
21
DRAM is ready for any valid command
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Operations
Figure 20:
INITIALIZATION Timing Diagram
((
))
VDD
VDDQ
((
))
tVTD1
VTT1
((
))
VREF
((
))
CK#
((
))
((
))
T1
T0
CK
tIS
CKE
LVCMOS
LOW level ( (
))
Command
((
))
((
))
tCH
tIH
tCL
tIS tIH
NOP
PRE
tCK
Ta0
Tb0
Tc0
Td0
Te0
Tf0
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
DM
((
))
((
))
((
))
((
))
Address
((
))
((
))
((
))
((
))
A10
((
))
((
))
All banks ( (
))
((
tIS tIH ) )
BA0, BA1
((
))
((
))
((
))
((
))
DQS
((
))
High-Z
((
))
DQ
((
))
High-Z
((
))
LMR
((
))
((
))
LMR
((
))
((
))
((
))
((
))
PRE
((
))
((
))
AR
((
))
((
))
AR
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
ACT2
tIS tIH
Code
((
))
((
))
Code3
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
RA
((
))
((
))
Code
( ( All banks
))
((
))
tIS tIH
((
))
((
))
((
))
((
))
((
))
((
))
RA
((
))
((
))
BA0 = 0
BA1 = 0
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tRP
tRFC
tRFC
tIS tIH
Code
tIS tIH
BA0 = 1
BA1 = 0
T = 200µs
Power-up: VDD and CK stable
Notes:
tRP
tMRD
tMRD
Load extended
mode register
Load mode
register5
200 cycles of CK4
Indicates A Break in
Time Scale
Don’t Care
1. VTT is not applied directly to the device; however, tVTD ≥ 0 to avoid device latch-up. VDDQ,
VTT, and VREF ≤ VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power-up,
even if VDD/VDDQ are 0V, provided a minimum of 42Ω of series resistance is used between
the VTT supply and the input pin. Once initialized, VREF must always be powered within the
specified range.
2. Although not required by the Micron device, JEDEC specifies issuing another LMR command
(A8 = 0) prior to activating any bank. If another LMR command is issued, the same, previously issued operating parameters must be used.
3. The two AUTO REFRESH commands at Td0 and Te0 may be applied following the LMR command at Ta0.
4. tMRD is required before any command can be applied (during MRD time only NOPs or
DESELECTs are allowed), and 200 cycles of CK are required before a READ command can be
issued.
5. While programming the operating parameters, reset the DLL with A8 = 1.
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
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1Gb: x4, x8, x16 DDR SDRAM
Operations
REGISTER DEFINITION
Mode Register
The mode register is used to define the specific DDR SDRAM mode of operation. This
definition includes the selection of a burst length, a burst type, a CAS latency, and an
operating mode, as shown in Figure 21. The mode register is programmed via the LMR
command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is
programmed again or until the device loses power (except for bit A8, which is selfclearing).
Reprogramming the mode register will not alter the contents of the memory, provided it
is performed correctly. The mode register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements will result in
unspecified operation.
Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4–A6 specify the CAS latency, and A7–An specify the operating
mode.
Figure 21:
Mode Register Definition
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
BA1 BA0 An . . .
n + 2 n + 1 n1 . . .
0
9
8
7
Operating mode
0
6
5
4
3
2
1
0
Mode register
(Mx)
CAS Latency BT Burst length
M2 M1 M0 Burst Length
Mn + 2 Mn + 1 Mode Register Definition
0
0
Base mode register
0
1
Extended mode register
1
0
1
1
M3
Burst Type
Reserved
0
Sequential
Reserved
1
Interleaved
Mn . . . M9 M8 M7 M6–M0 Operating Mode
Notes:
0
0
0
0
0
Valid
Normal operation
0
0
0
1
0
Valid
Normal operation/reset DLL
–
–
–
–
–
–
All other states reserved
0
0
0
Reserved
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M6
M5
M4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3 (-5B only)
1
0
0
Reserved
1
0
1
Reserved
1
1
0
2.5
1
1
1
Reserved
1. n is the most significant row address bit from Table 2 on page 2.
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1Gb: x4, x8, x16 DDR SDRAM
Operations
Burst Length (BL)
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length
being programmable for both READ and WRITE bursts, as shown in Figure 21 on
page 46. The burst length determines the maximum number of column locations that
can be accessed for a given READ or WRITE command. BL = 2, BL = 4, or BL = 8 locations
are available for both the sequential and the interleaved burst types. Reserved states
should not be used, as unknown operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block—
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1–Ai when BL = 2, by A2–Ai when BL = 4, and by A3–Ai when
BL = 8 (where Ai is the most significant column address bit for a given configuration).
The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. For example: for BL = 8, A3–Ai select the eight-data-element block; A0–
A2 select the first access within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type,
and the starting column address, as shown in Table 28.
Table 28:
Burst Definition
Order of Accesses Within a Burst
Burst Length
2
4
8
Starting Column Address
–
–
–
–
–
–
–
–
A2
0
0
0
0
1
1
1
1
–
–
–
A1
0
0
1
1
A1
0
0
1
1
0
0
1
1
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
Type = Sequential
Type = Interleaved
–
0-1
1-0
–
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
–
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
–
0-1
1-0
–
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
–
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
47
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1Gb: x4, x8, x16 DDR SDRAM
Operations
CAS Latency (CL)
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first bit of output data. The latency can be set to 2, 2.5, or 3 (-5B
only) clocks, as shown in Figure 22. Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Table 29 on page 49 indicates the operating frequencies at which each CL setting can be used.
Figure 22:
CAS Latency
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
CK#
CK
Command
NOP
CL = 2
DQS
DQ
T0
T1
T2
T2n
T3
READ
NOP
NOP
NOP
T3n
CK#
CK
Command
CL = 2.5
DQS
DQ
T0
T1
T2
T3
READ
NOP
NOP
NOP
T3n
CK#
CK
Command
CL = 3
DQS
DQ
Transitioning Data
Note:
Don’t Care
BL = 4 in the cases shown; shown with nominal tAC, tDQSCK, and tDQSQ.
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1Gb: x4, x8, x16 DDR SDRAM
Operations
Table 29:
CAS Latency
Allowable Operating Clock Frequency (MHz)
Speed
CL = 2
CL = 2.5
CL = 3
-5B
75 ≤ f ≤ 133
75 ≤ f ≤ 167
133 ≤ f ≤ 200
-6T
75 ≤ f ≤ 133
75 ≤ f ≤ 167
–
-75
75 ≤ f ≤ 100
75 ≤ f ≤ 133
–
Operating Mode
The normal operating mode is selected by issuing an LMR command with bits A7–An
each set to zero and bits A0–A6 set to the desired values. A DLL reset is initiated by
issuing an LMR command with bits A7 and A9–An each set to zero, bit A8 set to one, and
bits A0–A6 set to the desired values. Although not required by the Micron device, JEDEC
specifications recommend that an LMR command resetting the DLL should always be
followed by an LMR command selecting normal operating mode.
All other combinations of values for A7–An are reserved for future use and/or test
modes. Test modes and reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
Extended Mode Register
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable and output drive strength.
These functions are controlled via the bits shown in Figure 23 on page 50. The extended
mode register is programmed via the LMR command to the mode register (with BA0 = 1
and BA1 = 0) and will retain the stored information until it is programmed again or until
the device loses power. The enabling of the DLL should always be followed by an LMR
command to the mode register (BA0/BA1 = 0) to reset the DLL. The extended mode
register must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating any subsequent operation.
Violating either requirement could result in an unspecified operation.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. The x16
supports a programmable option for reduced drive. This option is intended for the
support of the lighter load and/or point-to-point environments. The selection of the
reduced drive strength will alter the DQ and DQS pins from SSTL_2, Class II drive
strength to a reduced drive strength, which is approximately 54 percent of the SSTL_2,
Class II drive strength.
DLL Enable/Disable
When the part is running without the DLL enabled, device functionality may be altered.
The DLL must be enabled for normal operation. DLL enable is required during powerup initialization and upon returning to normal operation after having disabled the DLL
for the purpose of debug or evaluation (when the device exits self refresh mode, the DLL
is enabled automatically). Anytime the DLL is enabled, 200 clock cycles with CKE HIGH
must occur before a READ command can be issued.
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1Gb: x4, x8, x16 DDR SDRAM
Operations
Figure 23:
Extended Mode Register Definition
BA1
BA0
An . . . A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
n + 2 n + 1 n1 . . . 9 8 7 6 5
Operating Mode
0
1
Mn + 2 Mn + 1
3
Mode Register Definition
2
1 0
DS DLL
DLL
0
Enable
1
Disable
0
Base mode register
0
1
Extended mode register
1
0
Reserved
0
Normal
1
1
Reserved
1
Reduced
2
Drive Strength
E1
3
Extended mode
register (Ex)
E0
0
En . . . E9 E8 E7 E6 E5 E4 E3 E2
Notes:
4
Address bus
E1, E0
Operating Mode
0
0
0
0
0
0
0
0
0
0
Valid
Reserved
–
–
–
–
–
–
–
–
–
–
–
Reserved
1. n is the most significant row address bit from Table 2 on page 2.
2. The reduced drive strength option is available only on the x16 version. The reduced drive
strength option is not supported on the x4 and x8 versions; contact Micron for future support of this feature.
3. The QFC# option is not supported.
ACTIVE
After a row is opened with an ACTIVE command, a READ or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 133 MHz clock (7.5ns period)
results in 2.7 clocks rounded to 3. This is reflected in Figure 24 on page 51, which covers
any case where 2 < tRCD (MIN)/tCK ≤ 3 (Figure 24 also shows the same case for tRRD; the
same procedure is used to convert other specification limits from time units to clock
cycles).
A row remains active (or open) for accesses until a PRECHARGE command is issued to
that bank. A PRECHARGE command must be issued before opening a different row in
the same bank.
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
RRD.
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1Gb: x4, x8, x16 DDR SDRAM
Operations
Figure 24:
Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK ≤ 3
T0
T1
T2
NOP
NOP
T3
T4
T5
T6
T7
NOP
NOP
RD/WR
NOP
CK#
CK
Command
ACT
Address
Row
Row
Col
Bank x
Bank y
Bank y
BA0, BA1
ACT
tRRD
tRCD
Don’t Care
READ
During the READ command, the value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the READ burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
Note:
For the READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out
element will be valid nominally at the next positive or negative clock edge (that is, at the
next crossing of CK and CK#). Figure 25 on page 53 shows the general timing for each
possible CL setting. DQS is driven by the DDR SDRAM along with output data. The
initial LOW state on DQS is known as the read preamble; the LOW state coincident with
the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z. Detailed explanations of tDQSQ (valid data-out skew), tQH (data-out
window hold), and the valid data window are depicted in Figure 33 on page 61 and
Figure 34 on page 62. Detailed explanations of tDQSCK (DQS transition skew to CK) and
t
AC (data-out transition skew to CK) are depicted in Figure 35 on page 63.
Data from any READ burst may be concatenated or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The
first data element from the new burst follows either the last element of a completed
burst or the last desired data element of a longer burst which is being truncated. The
new READ command should be issued x cycles after the first READ command, where x
equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 26 on page 54. A READ command can be initiated
on any clock cycle following a previous READ command. Nonconsecutive read data is
illustrated in Figure 27 on page 55. Full-speed random read accesses within a page (or
pages) can be performed, as shown in Figure 28 on page 56.
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1Gb: x4, x8, x16 DDR SDRAM
Operations
Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure 29 on page 57. The BURST TERMINATE latency is equal to the CL, that
is, the BURST TERMINATE command should be issued x cycles after the READ
command where x equals the number of desired data element pairs (pairs are required
by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 30 on page 58. The tDQSS (NOM) case is shown; the
t
DQSS (MAX) case has a longer bus idle time. (tDQSS [MIN] and tDQSS [MAX] are
defined in the section on WRITEs.) A READ burst may be followed by, or truncated with,
a PRECHARGE command to the same bank provided that auto precharge was not activated.
The PRECHARGE command should be issued x cycles after the READ command, where
x equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 31 on page 59. Following the PRECHARGE
command, a subsequent command to the same bank cannot be issued until both tRAS
and tRP have been met. Part of the row precharge time is hidden during the access of the
last data elements.
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1Gb: x4, x8, x16 DDR SDRAM
Operations
Figure 25:
READ Burst
CK#
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
T4
T5
NOP
NOP
T4
T5
NOP
NOP
CK
Command
Address
NOP
Bank a,
Col n
CL = 2
DQS
DO
n
DQ
T0
T1
T2
Command
READ
NOP
NOP
Address
Bank a,
Col n
T2n
T3
T3n
CK#
CK
NOP
CL = 2.5
DQS
DO
n
DQ
T0
T1
T2
T3
Command
READ
NOP
NOP
NOP
Address
Bank a,
Col n
T3n
T4
T4n
T5
CK#
CK
NOP
NOP
CL = 3
DQS
DO
n
DQ
Transitioning Data
Notes:
1.
2.
3.
4.
Don’t Care
DO n = data-out from column n.
BL = 4.
Three subsequent elements of data-out appear in the programmed order following DO n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
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1Gb: x4, x8, x16 DDR SDRAM
Operations
Figure 26:
Consecutive READ Bursts
T0
T1
T2
Command
READ
NOP
READ
Address
Bank,
Col n
CK#
T2n
T3
T3n
T4
T4n
T5
T5n
CK
NOP
NOP
NOP
Bank,
Col b
CL = 2
DQS
DO
n
DQ
T0
T1
T2
Command
READ
NOP
READ
Address
Bank,
Col n
CK#
DO
b
T2n
T3
T3n
T4
T4n
T5
T5n
CK
NOP
NOP
NOP
Bank,
Col b
CL = 2.5
DQS
DO
n
DQ
DO
b
T0
T1
T2
T3
Command
READ
NOP
READ
NOP
Address
Bank,
Col n
T3n
T4
T4n
T5
T5n
CK#
CK
NOP
NOP
Bank,
Col b
CL = 3
DQS
DO
n
DQ
DO
b
Transitioning Data
Notes:
Don’t Care
1. DO n (or b) = data-out from column n (or column b).
2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts
the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. Example applies only when READ commands are issued to same device.
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1Gb: x4, x8, x16 DDR SDRAM
Operations
Figure 27:
Nonconsecutive READ Bursts
T0
T1
T2
Command
READ
NOP
NOP
Address
Bank,
Col n
T2n
T3
T3n
T4
T5
NOP
NOP
T5n
T6
CK#
CK
READ
NOP
Bank,
Col b
CL = 2
DQS
DO
n
DQ
T0
T1
T2
Command
READ
NOP
NOP
Address
Bank,
Col n
DO
b
T2n
T3
T3n
T4
T5
NOP
NOP
T5n
T6
CK#
CK
READ
NOP
Bank,
Col b
CL = 2.5
DQS
DO
n
DQ
DO
b
T0
T1
T2
T3
T3n
Command
READ
NOP
NOP
READ
Address
Bank,
Col n
T4n
T4
T5
T6
NOP
NOP
CK#
CK
NOP
Bank,
Col b
CL = 3
DQS
DO
n
DQ
DO
b
Transitioning Data
Notes:
Don’t Care
1. DO n (or b) = data-out from column n (or column b).
2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts
the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
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1Gb: x4, x8, x16 DDR SDRAM
Operations
Figure 28:
Random READ Accesses
T0
T1
Command
READ
READ
READ
Address
Bank,
Col n
Bank,
Col x
Bank,
Col b
CK#
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CK
READ
NOP
NOP
Bank,
Col g
CL = 2
DQS
DO
n
DQ
DO
n'
T2n
DO
x
T0
T1
T2
T3
Command
READ
READ
READ
READ
Address
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
DO
x'
T3n
DO
b
T4
DO
b'
T4n
DO
g
T5
T5n
CK#
CK
NOP
NOP
CL = 2.5
DQS
DO
n
DQ
DO
n'
T0
T1
T2
T3
Command
READ
READ
READ
READ
Address
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
CK#
DO
x
T3n
DO
x'
T4
DO
b
T4n
DO
b'
T5
T5n
CK
NOP
NOP
CL = 3
DQS
DO
n
DQ
DO
n'
DO
x
Transitioning Data
Notes:
1.
2.
3.
4.
5.
DO
x'
DO
b
DO
b'
Don’t Care
DO n (or x or b or g) = data-out from column n (or column x or column b or column g).
BL = 2, BL = 4, or BL = 8 (if BL = 4 or BL = 8, the following burst interrupts the previous).
n', x', b', or g' indicate the next data-out following DO n, DO x, DO b, or DO g, respectively.
READs are to an active row in any bank.
Shown with nominal tAC, tDQSCK, and tDQSQ.
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Operations
Figure 29:
Terminating a READ Burst
T0
T1
T2
READ
BST1
NOP
T2n
T3
T4
T5
NOP
NOP
NOP
T3
T4
T5
NOP
NOP
NOP
T4
T5
NOP
NOP
CK#
CK
Command
Address
Bank a,
Col n
CL = 2
DQS
DO
n
DQ
T0
T1
T2
READ
BST1
NOP
T2n
CK#
CK
Command
Address
Bank a,
Col n
CL = 2.5
DQS
DO
n
DQ
T0
T1
T2
T3
READ
BST1
NOP
NOP
T3n
CK#
CK
Command
Address
Bank a,
Col n
CL = 3
DQS
DO
n
DQ
Transitioning Data
Notes:
1.
2.
3.
4.
5.
Don’t Care
Page remains open.
DO n = data-out from column n.
BL = 4.
Subsequent element of data-out appears in the programmed order following DO n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
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Operations
Figure 30:
READ-to-WRITE
T0
T1
T2
T2n
T3
T4
T4n
T5
T5n
CK#
CK
Command
READ
Address
Bank,
Col n
1
NOP
BST
WRITE
NOP
NOP
Bank,
Col b
tDQSS
(NOM)
CL = 2
DQS
DO
n
DQ
DI
b
DM
T0
T1
Command
READ
BST
Address
Bank,
Col n
T2
T2n
T3n
T3
T4
T5
T5n
CK#
CK
1
NOP
NOP
WRITE
NOP
Bank,
Col b
tDQSS
(NOM)
CL = 2.5
DQS
DO
n
DQ
DI
b
DM
T0
T1
T2
T3
READ
BST1
NOP
NOP
T3n
T4
T5
T5n
CK#
CK
Command
WRITE
NOP
Bank a,
Col n
Address
tDQSS
(NOM)
CL = 3
DQS
DO
n
DQ
DI
b
DM
Transitioning Data
Notes:
1.
2.
3.
4.
5.
6.
Don’t Care
Page remains open.
DO n = data-out from column n; DI b = data-in from column b.
BL = 4 (applies for bursts of 8 as well; if BL = 2, the BURST command shown can be NOP).
One subsequent element of data-out appears in the programmed order following DO n.
Data-in elements are applied following DI b in the programmed order.
Shown with nominal tAC, tDQSCK, and tDQSQ.
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Operations
Figure 31:
READ-to-PRECHARGE
T0
T1
READ
NOP
T2
T2n
T3
T3n
T4
T5
CK#
CK
Command
Address
PRE
Bank a,
Col n
NOP
NOP
ACT
Bank a,
(a or all)
Bank a,
Row
tRP
CL = 2
DQS
DO
n
DQ
T0
T1
T2
READ
NOP
PRE
T2n
T3
T3n
T4
T5
NOP
ACT
CK#
CK
Command
Address
NOP
Bank a,
(a or all)
Bank a,
Col n
Bank a,
Row
tRP
CL = 2.5
DQS
DO
n
DQ
T0
T1
T2
T3
READ
NOP
PRE
NOP
T3n
T4
T4n
T5
CK#
CK
Command
Address
NOP
Bank a,
(a or all)
Bank a,
Col n
CL = 3
ACT
Bank a,
Row
tRP
DQS
DO
n
DQ
Transitioning Data
Notes:
Don’t Care
1. Provided tRAS (MIN) is met, a READ command with auto precharge enabled would cause a
precharge to be performed at x number of clock cycles after the READ command, where
x = BL/2.
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DO n.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
assumed that tRAS (MIN) is met.
7. An ACTIVE command to the same bank is only allowed if tRC (MIN) is met.
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Operations
Figure 32:
Bank READ – Without Auto Precharge
CK#
T1
T0
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
Command
1
NOP
ACT
tIS
NOP
READ
NOP
1
3
1
PRE
1
NOP
NOP
Col n
tIS
A10
2
ACT
tIH
Row
Address
1
Row
tIH
All banks
4
Row
Row
One bank
tIS
BA0, BA1
tIH
Bank x
5
Bank x
tRCD
Bank x
Bank x
CL = 2
tRAS3
tRP
tRC
DM
Case 1: tAC (MIN) and tDQSCK (MIN)
tRPRE
tDQSCK (MIN)
tRPST
DQS
tLZ (MIN)
DO
n
DQ
tLZ (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
tRPRE
tAC (MIN)
tDQSCK (MAX)
tRPST
DQS
DO
n
DQ
tAC (MAX)
tHZ (MAX)
Transitioning Data
Notes:
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. The PRECHARGE command can only be applied at T5 if tRAS (MIN) is met.
4. Disable auto precharge.
5. “Don’t Care” if A10 is HIGH at T5.
6. DO n (or b) = data-out from column n (or column b); subsequent elements are provided in
the programmed order.
7. Refer to Figure 33 on page 61, Figure 34 on page 62, and Figure 35 on page 63 for detailed
DQS and DQ timing.
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Operations
Figure 33:
x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window
T1
T2
T2n
T3
T3n
T4
CK#
CK
tHP1
tHP1
tDQSQ2
DQS
tHP1
tHP1
tDQSQ2
tHP1
tHP1
tDQSQ2
tDQSQ2
tQH5
tQH5
3
DQ (last data valid)
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ (first data no longer valid)
tQH5
tQH5
DQ (last data valid)
T2
T2n
T3
T3n
DQ (first data no longer valid)
T2
T2n
T3
T3n
6
All DQ and DQS collectively
T2
T2n
T3
T3n
Data
valid
window
Data
valid
window
Data
valid
window
Earliest signal transition
Latest signal transition
Notes:
1.
2.
3.
4.
5.
6.
Data
valid
window
tHP
is the lesser of tCL or tCH clock transition collectively when a bank is active.
is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transition, and ends with the last valid DQ transition.
DQ transitioning after DQS transition define the tDQSQ window. DQS transitions at T2 and
T2n are an “early DQS”; at T3, a “nominal DQS”; and at T3n, a “late DQS”.
For a x4, only two DQ apply.
t
QH is derived from tHP: tQH = tHP - tQHS.
The data valid window is derived for each DQS transitions and is defined as tQH - tDQSQ.
tDQSQ
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Operations
Figure 34:
x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window
T1
T2
T2n
T3
T3n
T4
CK#
CK
tHP1
tHP1
tHP1
tHP1
tDQSQ2
tDQSQ2
tQH5
tQH5
tHP1
tHP1
tDQSQ2
tDQSQ2
tQH5
tQH5
LDQS3
4
DQ (last data valid)
4
4
DQ
4
DQ
4
DQ
4
DQ
4
DQ
4
DQ (first data no longer valid)
DQ
Lower byte
4
T2
T2n
T3
T3n
4
DQ (first data no longer valid)
T2
T2n
T3
T3n
6
DQ0–DQ7 and LDQS collectively
T2
T3
T3n
Data valid
window
Data valid
window
DQ (last data valid)
T2n
Data valid
window
Data valid
window
tDQSQ2
tDQSQ2
tDQSQ2
tDQSQ2
tQH5
tQH5
tQH5
tQH5
3
UDQS
7
DQ (last data valid)
Upper byte
7
DQ
7
DQ
7
DQ
7
DQ
7
DQ
7
DQ
7
DQ (first data no longer valid)
7
T2
T2n
7
DQ (first data no longer valid)
T2
T2n
6
DQ8–DQ15 and UDQS collectively
T2
DQ (last data valid)
Data valid
window
Notes:
1.
2.
3.
4.
5.
6.
7.
T2n
Data valid
window
T3
T3
T3
Data valid
window
T3n
T3n
T3n
Data valid
window
tHP
is the lesser of tCL or tCH clock transition collectively when a bank is active.
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transition, and ends with the last valid DQ transition.
DQ transitioning after DQS transition define the tDQSQ window. LDQS defines the lower
byte, and UDQS defines the upper byte.
DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
tQH is derived from tHP: tQH = tHP - tQHS.
The data valid window is derived for each DQS transition and is tQH - tDQSQ.
DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
t
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Operations
Figure 35:
Data Output Timing – tAC and tDQSCK
T01
CK#
T1
T2
T3
T2n
T3n
T4
T4n
CK
T5n
tRPST
tRPRE
DQS or LDQS/UDQS3
T6
t
tDQSCK2 (MAX) HZ (MAX)
tDQSCK2 (MIN)
tDQSCK2 (MAX)
tDQSCK2 (MIN)
tLZ (MIN)
T5
DQ (last data valid)
T2
T2n
T3
T3n
T4
T4n
T5
T5n
DQ (first data valid)
T2
T2n
T3
T3n
T4
T4n
T5
T5n
All DQ values collectively4
T2
T2n
T3
T3n
T4
T4n
T5
T5n
tLZ (MIN)
Notes:
tAC5 (MIN)
tAC5 (MAX)
tHZ (MAX)
1. READ command with CL = 2 issued at T0.
2. tDQSCK is the DQS output window relative to CK and is the “long term” component of the
DQS skew.
3. DQ transitioning after DQS transition define the tDQSQ window.
4. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
5. tAC is the DQ output window relative to CK and is the “long term” component of DQ skew.
6. tLZ (MIN) and tAC (MIN) are the first valid signal transitions.
7. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.
WRITE
During a WRITE command, the value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the WRITE burst (after tWR time); if auto precharge is not
selected, the row will remain open for subsequent accesses.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW, the
corresponding data will be written to memory. If the DM signal is registered HIGH, the
corresponding data inputs will be ignored, and a WRITE will not be executed to that
byte/column location.
Note:
For the WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first corresponding rising edge of DQS
(tDQSS) is specified with a relatively wide range (from 75 percent to 125 percent of one
clock cycle). All of the WRITE diagrams show the nominal case, and where the two
extreme cases (that is, tDQSS [MIN] and tDQSS [MAX]) might not be intuitive; they have
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Operations
also been included. Figure 36 on page 65 shows the nominal case and the extremes of
t
DQSS for BL = 4. Upon completion of a burst, assuming no other commands have been
initiated, the DQ will remain High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with or truncated with a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied after
either the last element of a completed burst or the last desired data element of a longer
burst which is being truncated. The new WRITE command should be issued x cycles
after the first WRITE command, where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architecture).
Figure 37 on page 66 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 38 on page 67. Full-speed random write accesses within a
page or pages can be performed as shown in Figure 39 on page 67.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE without truncating the WRITE burst, tWTR should be met, as shown in Figure 40
on page 68.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
in Figure 41 on page 69.
Note that only the data-in pairs that are registered prior to the tWTR period are written
to the internal array, and any subsequent data-in should be masked with DM, as shown
in Figure 42 on page 70.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst, tWR should be met, as shown in
Figure 43 on page 71.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 44 on page 72 and Figure 45 on page 73. Only the data-in pairs registered prior to the tWR period are written to the internal array; any subsequent data-in
should be masked with DM, as shown in Figures 44 and 45. After the PRECHARGE
command, a subsequent command to the same bank cannot be issued until tRP is met.
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Operations
Figure 36:
WRITE Burst
T0
T1
T2
Command
WRITE
NOP
NOP
Address
Bank a,
Col b
T2n
T3
CK#
CK
NOP
tDQSS (NOM)
DQS
tDQSS
DI
b
DQ
DM
tDQSS (MIN)
DQS
DQ
tDQSS
DI
b
DM
tDQSS (MAX)
DQS
tDQSS
DI
b
DQ
DM
Transitioning Data
Notes:
1.
2.
3.
4.
Don’t Care
DI b = data-in for column b.
Three subsequent elements of data-in are applied in the programmed order following DI b.
An uninterrupted burst of 4 is shown.
A10 is LOW with the WRITE command (auto precharge is disabled).
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Operations
Figure 37:
Consecutive WRITE-to-WRITE
T0
T1
Command
WRITE
NOP
Address
Bank,
Col b
T1n
T2
T2n
T3
T3n
T4
T4n
T5
CK#
CK
tDQSS (NOM)
WRITE
NOP
NOP
NOP
Bank,
Col n
tDQSS
DQS
DQ
DI
b
DI
n
DM
Transitioning Data
Notes:
1.
2.
3.
4.
5.
Don’t Care
DI b (or n) = data-in from column b (or column n).
Three subsequent elements of data-in are applied in the programmed order following DI b.
Three subsequent elements of data-in are applied in the programmed order following DI n.
An uninterrupted burst of 4 is shown.
Each WRITE command may be to any bank.
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Operations
Figure 38:
Nonconsecutive WRITE-to-WRITE
T0
T1
Command
WRITE
NOP
Address
Bank,
Col b
T1n
T2
T2n
T3
T4
T4n
T5
T5n
CK#
CK
NOP
WRITE
NOP
NOP
Bank,
Col n
tDQSS
tDQSS (NOM)
DQS
DI
n
DI
b
DQ
DM
Transitioning Data
Notes:
Figure 39:
1.
2.
3.
4.
5.
Don’t Care
DI b (or n) = data-in from column b (or column n).
Three subsequent elements of data-in are applied in the programmed order following DI b.
Three subsequent elements of data-in are applied in the programmed order following DI n.
An uninterrupted burst of 4 is shown.
Each WRITE command may be to any bank.
Random WRITE Cycles
T0
T1
T1n
T2
T2n
T3
T3n
T4
Command
WRITE
WRITE
WRITE
WRITE
WRITE
Address
Bank,
Col b
Bank,
Col x
Bank,
Col n
Bank,
Col a
Bank,
Col g
T4n
T5
T5n
CK#
CK
NOP
tDQSS (NOM)
DQS
DQ
DI
b
DI
b'
DI
x
DI
x'
DI
n
DI
n'
DI
a
DI
a'
DI
g
DI
g'
DM
Transitioning Data
Notes:
Don’t Care
1. DI b (or x or n or a or g) = data-in from column b (or column x, or column n, or column a, or
column g).
2. b', x', n', a' or g' indicate the next data-in following DO b, DO x, DO n, DO a, or DO g,
respectively.
3. Programmed BL = 2, BL = 4, or BL = 8 in cases shown.
4. Each WRITE command may be to any bank.
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Operations
Figure 40:
WRITE-to-READ – Uninterrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
T6
T6n
NOP
READ
NOP
NOP
CK#
CK
Command
NOP
tWTR
Bank a,
Col b
Address
tDQSS (NOM)
Bank a,
Col n
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
tDQSS (MIN)
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
tDQSS (MAX)
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
Transitioning Data
Notes:
Don’t Care
1.
2.
3.
4.
5.
DI b = data-in for column b; DO n = data-out for column n.
Three subsequent elements of data-in are applied in the programmed order following DI b.
An uninterrupted burst of 4 is shown.
tWTR is referenced from the first positive CK edge after the last data-in pair.
The READ and WRITE commands are to the same device. However, the READ and WRITE
commands may be to different devices, in which case tWTR is not required, and the READ
command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
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Operations
Figure 41:
WRITE-to-READ – Interrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T5
NOP
NOP
T5n
T6
T6n
CK#
CK
Command
NOP
READ
NOP
tWTR
Bank a,
Col b
Address
tDQSS (NOM)
Bank a,
Col n
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
tDQSS (MIN)
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
tDQSS (MAX)
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
Transitioning Data
Notes:
1.
2.
3.
4.
5.
6.
7.
Don’t Care
DI b = data-in for column b; DO n = data-out for column n.
An interrupted burst of 4 is shown; two data elements are written.
One subsequent element of data-in is applied in the programmed order following DI b.
tWTR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T2 and T2n (nominal case) to register DM.
If the burst of 8 is used, DM and DQS are required at T3 and T3n because the READ command will not mask these two data elements.
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Operations
Figure 42:
WRITE-to-READ – Odd Number of Data, Interrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3n
T3
T4
T5
NOP
NOP
T5n
T6
T6n
CK#
CK
Command
NOP
READ
NOP
tWTR
Bank a,
Col b
Address
tDQSS (NOM)
Bank a,
Col n
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
tDQSS (MIN)
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
tDQSS (MAX)
tDQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
Transitioning Data
Notes:
Don’t Care
1.
2.
3.
DI b = data-in for column b; DO n = data-out for column n.
An interrupted burst of 4 is shown; one data element is written.
t
WTR is referenced from the first positive CK edge after the last desired data-in pair (not
the last two data elements).
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 is used, DM and DQS are required at T3–T3n because the READ command
will not mask these data elements.
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Operations
Figure 43:
WRITE-to-PRECHARGE – Uninterrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
NOP
PRE
T6
CK#
CK
Command
NOP
NOP
Bank,
(a or all)
Bank a,
Col b
Address
tDQSS (NOM)
NOP
tRP
tWR
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MIN)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MAX)
tDQSS
DQS
DI
b
DQ
DM
Transitioning Data
Notes:
Don’t Care
1.
2.
3.
4.
5.
DI b = data-in for column b.
Three subsequent elements of data-in are applied in the programmed order following DI b.
An uninterrupted burst of 4 is shown.
tWR is referenced from the first positive CK edge after the last data-in pair.
The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE
and WRITE commands may be to different devices, in which case tWR is not required, and
the PRECHARGE command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
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Operations
Figure 44:
WRITE-to-PRECHARGE – Interrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
CK#
CK
Command
NOP
NOP
PRE
tDQSS (NOM)
NOP
Bank,
(a or all)
Bank a,
Col b
Address
NOP
tRP
tWR
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MIN)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MAX)
tDQSS
DQS
DI
b
DQ
DM
Transitioning Data
Notes:
1.
2.
3.
4.
5.
6.
7.
Don’t Care
DI b = data-in for column b.
Subsequent element of data-in is applied in the programmed order following DI b.
An interrupted burst of 8 is shown; two data elements are written.
tWR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T4 and T4n (nominal case) to register DM.
If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
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Operations
Figure 45:
WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
CK#
CK
Command
NOP
NOP
PRE
tDQSS (NOM)
NOP
Bank,
(a or all)
Bank a,
Col b
Address
NOP
tRP
tWR
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MIN)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MAX)
tDQSS
DQS
DI
b
DQ
DM
Transitioning Data
Notes:
1.
2.
3.
4.
5.
6.
Don’t Care
DI b = data-in for column b.
An interrupted burst of 8 is shown; one data element is written.
tWR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T4 and T4n (nominal case) to register DM.
If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
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Operations
Figure 46:
Bank WRITE – Without Auto Precharge
T1
T0
CK#
T2
T3
T4
WRITE2
NOP1
T4n
T5
T5n
T6
T7
T8
NOP1
NOP1
PRE
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
Command
NOP1
NOP1
ACT
tIS
Row
Address
Col n
tIS
A10
BA0, BA1
tIH
All banks
3
Row
tIS
NOP1
tIH
One bank
tIH
Bank x
Bank x4
Bank x
tWR
tRCD
tRP
tRAS
tDQSS (NOM)
DQS
tDQSL
tWPRES tWPRE
tDQSH tWPST
DI
b
DQ5
DM
tDS
tDH
Transitioning Data
Notes:
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. DI b = data-in from column b; subsequent elements are provided in the programmed order.
6. See Figure 48 on page 76 for detailed DQ timing.
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Operations
Figure 47:
WRITE – DM Operation
T1
T0
T2
T3
T4
T4n
T5
T5n
T6
T7
T8
CK#
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
Command
1
1
ACT
NOP
NOP
tIS
BA0, BA1
1
1
NOP
NOP
1
1
NOP
PRE
tIH
All banks
3
Row
tIS
NOP
Col n
tIS
A10
2
tIH
Row
Address
WRITE
One bank
tIH
Bank x
4
Bank x
Bank x
tWR
tRCD
tRP
tRAS
tDQSS (NOM)
DQS
tDQSL
tWPRES tWPRE
5
tDQSH
tWPST
DI
b
DQ
DM
tDS
tDH
Transitioning Data
Notes:
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. DI b = data-in from column b; subsequent elements are provided in the programmed order.
6. See Figure 48 on page 76 for detailed DQ timing.
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Operations
Figure 48:
Data Input Timing
1
T0
T1
T1n
T2
T2n
T3
CK#
CK
tDQSS
tDSH2
tDSS3
tDSH2
tDSS3
tDQSL
tDQSH
tWPST
DQS
tWPRES tWPRE
DI
b
DQ
DM
tDS
tDH
Transitioning Data
Notes:
1.
2.
3.
4.
5.
Don’t Care
WRITE command issued at T0.
(MIN) generally occurs during tDQSS (MIN).
tDSS (MIN) generally occurs during tDQSS (MAX).
For x16, LDQS controls the lower byte and UDQS controls the upper byte.
DI b = data-in from column b.
tDSH
PRECHARGE
The bank(s) will be available for a subsequent row access a specified time (tRP) after the
PRECHARGE command is issued, except in the case of concurrent auto precharge. With
concurrent auto precharge, a READ or WRITE command to a different bank is allowed as
long as it does not interrupt the data transfer in the current bank and does not violate
any other timing parameters. Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1
select the bank. When all banks are to be precharged, BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that bank. A PRECHARGE
command will be treated as a NOP if there is no open row in that bank (idle state), or if
the previously open row is already in the process of precharging.
Auto Precharge
Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is either enabled or disabled for each individual READ or WRITE
command. This device supports concurrent auto precharge if the command to the other
bank does not interrupt the data transfer to the current bank.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This “earliest valid stage” is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, without violating tRAS (MIN), as described for
each burst type in “Operations” on page 43. The user must not issue another command
to the same bank until the precharge time (tRP) is completed.
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Operations
Figure 49:
Bank READ – with Auto Precharge
T1
T0
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
CK#
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
Command
1
NOP
1
ACT
tIS
Address
Row
A10
Row
NOP
2,3
1
READ
1
NOP
NOP
1
1
NOP
NOP
ACT
tIH
Col n
Row
4
IS
BA0, BA1
tIS
tIH
Row
IH
Bank x
Bank x
tRCD, tRAP3
Bank x
CL = 2
tRAS
tRP5
tRC
DM
Case 1: tAC (MIN) and tDQSCK (MIN)
tDQSCK (MIN)
tRPRE
tRPST
DQS
tLZ (MIN)
DO
n
6
DQ
tLZ (MIN)
tAC (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
tRPRE
tDQSCK (MAX)
tRPST
DQS
DO
n
6
DQ
tAC (MAX)
tHZ (MAX)
Transitioning Data
Notes:
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. The READ command can only be applied at T3 if tRAP is satisfied at T3.
4. Enable auto precharge.
5. tRP starts only after tRAS has been satisfied.
6. DO n = data-out from column n; subsequent elements are provided in the programmed
order.
7. Refer to Figure 33 on page 61, Figure 34 on page 62, and Figure 35 on page 63 for detailed
DQS and DQ timing.
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Operations
Figure 50:
Bank WRITE – with Auto Precharge
T1
T0
T2
T3
T4
T4n
T5
T5n
T6
T7
T8
1
NOP
1
NOP
CK#
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
Command
1
NOP
NOP
ACT
tIS
1
1
NOP
2
WRITE
1
NOP
1
NOP
tIH
Address
Row
A10
Row
Col n
3
tIS
BA0, BA1
tIS
tIH
tIH
Bank x
Bank x
tWR
tRCD
tRP
tRAS
tDQSS (NOM)
DQS
tWPRES tWPRE
tDQSL
tDQSH
tWPST
DI
b
4
DQ
DM
tDS
tDH
Transitioning Data
Notes:
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. Enable auto precharge.
4. DI n = data-out from column n; subsequent elements are provided in the programmed
order.
5. See Figure 48 on page 76 for detailed DQ timing.
AUTO REFRESH
During auto refresh, the addressing is generated by the internal refresh controller. This
makes the address bits a “Don’t Care” during an AUTO REFRESH command. The DDR
SDRAM requires AUTO REFRESH cycles at an average interval of tREFI (MAX).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH
command is 9 × tREFI(= tREFC). JEDEC specifications only support 8 × tREFI; Micron
specifications exceed the JEDEC requirement by one clock. This maximum absolute
interval is to allow future support for DLL updates, internal to the DDR SDRAM, to be
restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between
updates.
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Operations
Although not a JEDEC requirement, to provide for future functionality features, CKE
must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period
begins when the AUTO REFRESH command is registered and ends tRFC later.
Figure 51:
Auto Refresh Mode
T0
T2
T1
T3
T4
CK#
CK
tIS tIH
tCH
CK
CKE
Valid
tIS
Command
tCL
tIH
NOP1
PRE
NOP1
NOP1
AR
Address
All banks
A10
One bank
tIS tIH
Bank(s)4
BA0, BA1
5
DQS
5
DQ
DM
5
tRP
((
))
((
))
((
))
((
))
((
))
((
))
Ta0
NOP1,2
Ta1
AR3
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tRFC
Tb0
Tb1
Tb2
NOP1
ACT
Valid
NOP1,2
RA
RA
BA
tRFC
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other valid commands may be possible at
these times. CKE must be active during clock-positive transitions.
2. NOP or COMMAND INHIBIT are the only commands allowed until after tRFC time; CKE must
be active during clock-positive transitions.
3. The second AUTO REFRESH is not required and is only shown as an example of two back-toback AUTO REFRESH commands.
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active
(that is, must precharge all active banks).
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for the operations shown.
SELF REFRESH
When in the self refresh mode, the DDR SDRAM retains data without external clocking.
The DLL is automatically disabled upon entering SELF REFRESH and is automatically
enabled upon exiting SELF REFRESH (a DLL reset and 200 clock cycles must then occur
before a READ command can be issued). Input signals except CKE are “Don’t Care”
during SELF REFRESH. VREF voltage is also required for the full duration of SELF
REFRESH.
The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK
and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for tXSNR because time is required for the
completion of any internal refresh in progress. A simple algorithm for meeting both
refresh and DLL requirements is to apply NOPs for tXSRD time, then a DLL RESET (via
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Operations
the extended mode register) and NOPs for 200 additional clock cycles before applying a
READ. Any command other than a READ can be performed tXSNR (MIN) after the DLL
reset. NOP or DESELECT commands must be issued during the tXSNR (MIN) time.
Figure 52:
Self Refresh Mode
T11
T0
CK#
CK1
tCH
tIS
tIH
tCL
tIS
Command2
Ta01
Ta1
Ta2
tCK
t IS
((
))
CKE
tIS
((
))
((
))
tIH
NOP
AR
((
))
((
))
NOP
NOP
Tb1
Tb2
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Valid3
tIS
Valid
((
))
((
))
Valid
Valid
((
))
((
))
Valid
tIH
Address
((
))
((
))
((
))
((
))
DQS
((
))
((
))
((
))
((
))
DQ
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
DM
tRP4
Tc1
Valid
tXSNR5
tXSRD6
Enter self refresh mode7
Notes:
Exit self refresh mode7
Don’t Care
1. Clock must be stable until after the SELF REFRESH command has been registered. A change
in clock frequency is allowed before Ta0, provided it is within the specified tCK limits.
Regardless, the clock must be stable before exiting self refresh mode—that is, the clock
must be cycling within specifications by Ta0.
2. NOPs are interchangeable with DESELECT commands.
3. AUTO REFRESH is not required at this point but is highly recommended.
4. Device must be in the all banks idle state prior to entering self refresh mode.
5. tXSNR is required before any non-READ command can be applied; that is only NOP or DESELECT commands are allowed until Tb1.
6. tXSRD (200 cycles of a valid clock with CKE = HIGH) is required before any READ command
can be applied.
7. As a general rule, any time self refresh mode is exited, the DRAM may not re-enter the self
refresh mode until all rows have been refreshed via the AUTO REFRESH command at the
distributed refresh rate, tREFI, or faster. However, the self refresh mode may be re-entered
anytime after exiting if each of the following conditions is met:
7a. The DRAM had been in the self refresh mode for a minimum of 200ms prior to exiting.
7b. tXSNR and tXSRD are not violated.
7c. At least two AUTO REFRESH commands are performed during each tREFI interval while
the DRAM remains out of self refresh mode.
8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.
9. Once the device is initialized, VREF must always be powered within specified range.
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
80
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Operations
Power-down (CKE Not Active)
Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in
progress, from the issuing of a READ or WRITE command, until completion of the
access. Thus a clock suspend is not supported. For READs, an access completion is
defined when the read postamble is satisfied; for WRITEs, when the write recovery time
(tWR) is satisfied.
Power-down, as shown in Figure 53 on page 82, is entered when CKE is registered LOW
and all criteria in Table 27 on page 38 are met. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when a
row is active in any bank, this mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CK, CK#, and CKE. For
maximum power savings, the DLL is frozen during precharge power-down mode. Exiting
power-down requires the device to be at the same voltage and frequency as when it
entered power-down. However, power-down duration is limited by the refresh requirements of the device (tREFC).
While in power-down, CKE LOW and a stable clock signal must be maintained at the
inputs of the DDR SDRAM, while all other input signals are “Don’t Care.” The powerdown state is synchronously exited when CKE is registered HIGH (in conjunction with a
NOP or DESELECT command). A valid executable command may be applied one clock
cycle later.
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
81
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR SDRAM
Operations
Figure 53:
Power-Down Mode
T0
T1
T2
CK#
CK
tCK
tIS
CKE
tIS
Ta2
tIS
((
))
tIH
Valid2
tIS
Address
tCL
Ta1
1
tIS
Command
tIH
tCH
Ta0
((
))
((
))
((
))
((
))
NOP
tIH
NOP
((
))
((
))
Valid
DQS
((
))
((
))
DQ
((
))
((
))
DM
((
))
((
))
Valid
Valid
tREFC
Enter 3
power-down
mode
Exit
power-down
mode
Don’t Care
Notes:
1. Once initialized, VREF must always be powered within the specified range.
2. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at
least one row is already active), then the power-down mode shown is active power-down.
3. No column accesses are allowed to be in progress at the time power-down is entered.
®
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Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth
herein. Although considered final, these specifications are subject to change, as further product development and data
characterization sometimes occur.
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DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
82
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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